1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch.h> 8*91f16700Schasinglulu #include <arch_features.h> 9*91f16700Schasinglulu #include <arch_helpers.h> 10*91f16700Schasinglulu #include <lib/extensions/pmuv3.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu static u_register_t mtpmu_disable_el3(u_register_t sdcr) 13*91f16700Schasinglulu { 14*91f16700Schasinglulu if (!is_feat_mtpmu_supported()) { 15*91f16700Schasinglulu return sdcr; 16*91f16700Schasinglulu } 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* 19*91f16700Schasinglulu * SDCR.MTPME = 0 20*91f16700Schasinglulu * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is 21*91f16700Schasinglulu * zero. 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu sdcr &= ~SDCR_MTPME_BIT; 24*91f16700Schasinglulu 25*91f16700Schasinglulu return sdcr; 26*91f16700Schasinglulu } 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* 29*91f16700Schasinglulu * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and 30*91f16700Schasinglulu * to not clash with platforms which reuse the PMU name 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu void pmuv3_init_el3(void) 33*91f16700Schasinglulu { 34*91f16700Schasinglulu u_register_t sdcr = read_sdcr(); 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* --------------------------------------------------------------------- 37*91f16700Schasinglulu * Initialise SDCR, setting all the fields rather than relying on hw. 38*91f16700Schasinglulu * 39*91f16700Schasinglulu * SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited 40*91f16700Schasinglulu * in Secure state. This bit is RES0 in versions of the architecture 41*91f16700Schasinglulu * earlier than ARMv8.5 42*91f16700Schasinglulu * 43*91f16700Schasinglulu * SDCR.SPME: Set to zero so that event counting is prohibited in Secure 44*91f16700Schasinglulu * state (and explicitly EL3 with later revisions). If ARMv8.2 Debug is 45*91f16700Schasinglulu * not implemented this bit does not have any effect on the counters 46*91f16700Schasinglulu * unless there is support for the implementation defined 47*91f16700Schasinglulu * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 48*91f16700Schasinglulu * --------------------------------------------------------------------- 49*91f16700Schasinglulu */ 50*91f16700Schasinglulu sdcr = (sdcr | SDCR_SCCD_BIT) & ~SDCR_SPME_BIT; 51*91f16700Schasinglulu sdcr = mtpmu_disable_el3(sdcr); 52*91f16700Schasinglulu write_sdcr(sdcr); 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* --------------------------------------------------------------------- 55*91f16700Schasinglulu * Initialise PMCR, setting all fields rather than relying 56*91f16700Schasinglulu * on hw. Some fields are architecturally UNKNOWN on reset. 57*91f16700Schasinglulu * 58*91f16700Schasinglulu * PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode. 59*91f16700Schasinglulu * 60*91f16700Schasinglulu * PMCR.X: Set to zero to disable export of events. 61*91f16700Schasinglulu * 62*91f16700Schasinglulu * PMCR.C: Set to one to reset PMCCNTR. 63*91f16700Schasinglulu * 64*91f16700Schasinglulu * PMCR.P: Set to one to reset each event counter PMEVCNTR<n> to zero. 65*91f16700Schasinglulu * 66*91f16700Schasinglulu * PMCR.E: Set to zero to disable cycle and event counters. 67*91f16700Schasinglulu * --------------------------------------------------------------------- 68*91f16700Schasinglulu */ 69*91f16700Schasinglulu 70*91f16700Schasinglulu write_pmcr(read_pmcr() | PMCR_DP_BIT | PMCR_C_BIT | PMCR_P_BIT | 71*91f16700Schasinglulu ~(PMCR_X_BIT | PMCR_E_BIT)); 72*91f16700Schasinglulu } 73