1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <travis.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* Hardware handled coherency */ 15*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 16*91f16700Schasinglulu#error "Travis must be compiled with HW_ASSISTED_COHERENCY enabled" 17*91f16700Schasinglulu#endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 64-bit only core */ 20*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 21*91f16700Schasinglulu#error "Travis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulucpu_reset_func_start travis 25*91f16700Schasinglulu /* ---------------------------------------------------- 26*91f16700Schasinglulu * Disable speculative loads 27*91f16700Schasinglulu * ---------------------------------------------------- 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu msr SSBS, xzr 30*91f16700Schasinglulucpu_reset_func_end travis 31*91f16700Schasinglulu 32*91f16700Schasinglulufunc travis_core_pwr_dwn 33*91f16700Schasinglulu#if ENABLE_SME_FOR_NS 34*91f16700Schasinglulu /* --------------------------------------------------- 35*91f16700Schasinglulu * Disable SME if enabled and supported 36*91f16700Schasinglulu * --------------------------------------------------- 37*91f16700Schasinglulu */ 38*91f16700Schasinglulu mrs x0, ID_AA64PFR1_EL1 39*91f16700Schasinglulu ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \ 40*91f16700Schasinglulu #ID_AA64PFR1_EL1_SME_WIDTH 41*91f16700Schasinglulu cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED 42*91f16700Schasinglulu b.eq 1f 43*91f16700Schasinglulu msr TRAVIS_SVCRSM, xzr 44*91f16700Schasinglulu msr TRAVIS_SVCRZA, xzr 45*91f16700Schasinglulu1: 46*91f16700Schasinglulu#endif 47*91f16700Schasinglulu /* --------------------------------------------------- 48*91f16700Schasinglulu * Enable CPU power down bit in power control register 49*91f16700Schasinglulu * --------------------------------------------------- 50*91f16700Schasinglulu */ 51*91f16700Schasinglulu sysreg_bit_set TRAVIS_IMP_CPUPWRCTLR_EL1, \ 52*91f16700Schasinglulu TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 53*91f16700Schasinglulu isb 54*91f16700Schasinglulu ret 55*91f16700Schasingluluendfunc travis_core_pwr_dwn 56*91f16700Schasinglulu 57*91f16700Schasingluluerrata_report_shim travis 58*91f16700Schasinglulu 59*91f16700Schasinglulu.section .rodata.travis_regs, "aS" 60*91f16700Schasinglulutravis_regs: /* The ASCII list of register names to be reported */ 61*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 62*91f16700Schasinglulu 63*91f16700Schasinglulufunc travis_cpu_reg_dump 64*91f16700Schasinglulu adr x6, travis_regs 65*91f16700Schasinglulu mrs x8, TRAVIS_IMP_CPUECTLR_EL1 66*91f16700Schasinglulu ret 67*91f16700Schasingluluendfunc travis_cpu_reg_dump 68*91f16700Schasinglulu 69*91f16700Schasingluludeclare_cpu_ops travis, TRAVIS_MIDR, \ 70*91f16700Schasinglulu travis_reset_func, \ 71*91f16700Schasinglulu travis_core_pwr_dwn 72