1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <context.h> 10*91f16700Schasinglulu#include <cpu_macros.S> 11*91f16700Schasinglulu#include <cpuamu.h> 12*91f16700Schasinglulu#include <rainier.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* Hardware handled coherency */ 15*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 16*91f16700Schasinglulu#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled" 17*91f16700Schasinglulu#endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 64-bit only core */ 20*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 21*91f16700Schasinglulu#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulu/* -------------------------------------------------- 25*91f16700Schasinglulu * Disable speculative loads if Rainier supports 26*91f16700Schasinglulu * SSBS. 27*91f16700Schasinglulu * 28*91f16700Schasinglulu * Shall clobber: x0. 29*91f16700Schasinglulu * -------------------------------------------------- 30*91f16700Schasinglulu */ 31*91f16700Schasinglulufunc rainier_disable_speculative_loads 32*91f16700Schasinglulu /* Check if the PE implements SSBS */ 33*91f16700Schasinglulu mrs x0, id_aa64pfr1_el1 34*91f16700Schasinglulu tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 35*91f16700Schasinglulu b.eq 1f 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* Disable speculative loads */ 38*91f16700Schasinglulu msr SSBS, xzr 39*91f16700Schasinglulu 40*91f16700Schasinglulu1: 41*91f16700Schasinglulu ret 42*91f16700Schasingluluendfunc rainier_disable_speculative_loads 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* Rainier R0P0 is based on Neoverse N1 R4P0. */ 45*91f16700Schasingluluworkaround_reset_start rainier, ERRATUM(1868343), ERRATA_N1_1868343 46*91f16700Schasinglulu sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13 47*91f16700Schasingluluworkaround_reset_end rainier, ERRATUM(1868343) 48*91f16700Schasinglulu 49*91f16700Schasinglulucheck_erratum_ls rainier, ERRATUM(1868343), CPU_REV(0, 0) 50*91f16700Schasinglulu 51*91f16700Schasinglulucpu_reset_func_start rainier 52*91f16700Schasinglulu bl rainier_disable_speculative_loads 53*91f16700Schasinglulu /* Forces all cacheable atomic instructions to be near */ 54*91f16700Schasinglulu sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2 55*91f16700Schasinglulu 56*91f16700Schasinglulu#if ENABLE_FEAT_AMU 57*91f16700Schasinglulu /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 58*91f16700Schasinglulu sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT 59*91f16700Schasinglulu 60*91f16700Schasinglulu /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 61*91f16700Schasinglulu sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* Enable group0 counters */ 64*91f16700Schasinglulu mov x0, #RAINIER_AMU_GROUP0_MASK 65*91f16700Schasinglulu msr CPUAMCNTENSET_EL0, x0 66*91f16700Schasinglulu#endif 67*91f16700Schasinglulucpu_reset_func_end rainier 68*91f16700Schasinglulu 69*91f16700Schasinglulu /* --------------------------------------------- 70*91f16700Schasinglulu * HW will do the cache maintenance while powering down 71*91f16700Schasinglulu * --------------------------------------------- 72*91f16700Schasinglulu */ 73*91f16700Schasinglulufunc rainier_core_pwr_dwn 74*91f16700Schasinglulu /* --------------------------------------------- 75*91f16700Schasinglulu * Enable CPU power down bit in power control register 76*91f16700Schasinglulu * --------------------------------------------- 77*91f16700Schasinglulu */ 78*91f16700Schasinglulu sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK 79*91f16700Schasinglulu isb 80*91f16700Schasinglulu ret 81*91f16700Schasingluluendfunc rainier_core_pwr_dwn 82*91f16700Schasinglulu 83*91f16700Schasingluluerrata_report_shim rainier 84*91f16700Schasinglulu 85*91f16700Schasinglulu /* --------------------------------------------- 86*91f16700Schasinglulu * This function provides Rainier specific 87*91f16700Schasinglulu * register information for crash reporting. 88*91f16700Schasinglulu * It needs to return with x6 pointing to 89*91f16700Schasinglulu * a list of register names in ascii and 90*91f16700Schasinglulu * x8 - x15 having values of registers to be 91*91f16700Schasinglulu * reported. 92*91f16700Schasinglulu * --------------------------------------------- 93*91f16700Schasinglulu */ 94*91f16700Schasinglulu.section .rodata.rainier_regs, "aS" 95*91f16700Schasinglulurainier_regs: /* The ascii list of register names to be reported */ 96*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 97*91f16700Schasinglulu 98*91f16700Schasinglulufunc rainier_cpu_reg_dump 99*91f16700Schasinglulu adr x6, rainier_regs 100*91f16700Schasinglulu mrs x8, RAINIER_CPUECTLR_EL1 101*91f16700Schasinglulu ret 102*91f16700Schasingluluendfunc rainier_cpu_reg_dump 103*91f16700Schasinglulu 104*91f16700Schasingluludeclare_cpu_ops rainier, RAINIER_MIDR, \ 105*91f16700Schasinglulu rainier_reset_func, \ 106*91f16700Schasinglulu rainier_core_pwr_dwn 107