1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <arch.h> 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <cpu_macros.S> 9*91f16700Schasinglulu#include <qemu_max.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulufunc qemu_max_core_pwr_dwn 12*91f16700Schasinglulu /* --------------------------------------------- 13*91f16700Schasinglulu * Disable the Data Cache. 14*91f16700Schasinglulu * --------------------------------------------- 15*91f16700Schasinglulu */ 16*91f16700Schasinglulu mrs x1, sctlr_el3 17*91f16700Schasinglulu bic x1, x1, #SCTLR_C_BIT 18*91f16700Schasinglulu msr sctlr_el3, x1 19*91f16700Schasinglulu isb 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* --------------------------------------------- 22*91f16700Schasinglulu * Flush L1 cache to L2. 23*91f16700Schasinglulu * --------------------------------------------- 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu mov x18, lr 26*91f16700Schasinglulu mov x0, #DCCISW 27*91f16700Schasinglulu bl dcsw_op_level1 28*91f16700Schasinglulu mov lr, x18 29*91f16700Schasinglulu ret 30*91f16700Schasingluluendfunc qemu_max_core_pwr_dwn 31*91f16700Schasinglulu 32*91f16700Schasinglulufunc qemu_max_cluster_pwr_dwn 33*91f16700Schasinglulu /* --------------------------------------------- 34*91f16700Schasinglulu * Disable the Data Cache. 35*91f16700Schasinglulu * --------------------------------------------- 36*91f16700Schasinglulu */ 37*91f16700Schasinglulu mrs x1, sctlr_el3 38*91f16700Schasinglulu bic x1, x1, #SCTLR_C_BIT 39*91f16700Schasinglulu msr sctlr_el3, x1 40*91f16700Schasinglulu isb 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* --------------------------------------------- 43*91f16700Schasinglulu * Flush all caches to PoC. 44*91f16700Schasinglulu * --------------------------------------------- 45*91f16700Schasinglulu */ 46*91f16700Schasinglulu mov x0, #DCCISW 47*91f16700Schasinglulu b dcsw_op_all 48*91f16700Schasingluluendfunc qemu_max_cluster_pwr_dwn 49*91f16700Schasinglulu 50*91f16700Schasingluluerrata_report_shim qemu_max 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* --------------------------------------------- 53*91f16700Schasinglulu * This function provides cpu specific 54*91f16700Schasinglulu * register information for crash reporting. 55*91f16700Schasinglulu * It needs to return with x6 pointing to 56*91f16700Schasinglulu * a list of register names in ascii and 57*91f16700Schasinglulu * x8 - x15 having values of registers to be 58*91f16700Schasinglulu * reported. 59*91f16700Schasinglulu * --------------------------------------------- 60*91f16700Schasinglulu */ 61*91f16700Schasinglulu.section .rodata.qemu_max_regs, "aS" 62*91f16700Schasingluluqemu_max_regs: /* The ascii list of register names to be reported */ 63*91f16700Schasinglulu .asciz "" /* no registers to report */ 64*91f16700Schasinglulu 65*91f16700Schasinglulufunc qemu_max_cpu_reg_dump 66*91f16700Schasinglulu adr x6, qemu_max_regs 67*91f16700Schasinglulu ret 68*91f16700Schasingluluendfunc qemu_max_cpu_reg_dump 69*91f16700Schasinglulu 70*91f16700Schasinglulu 71*91f16700Schasinglulu/* cpu_ops for QEMU MAX */ 72*91f16700Schasingluludeclare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \ 73*91f16700Schasinglulu qemu_max_core_pwr_dwn, \ 74*91f16700Schasinglulu qemu_max_cluster_pwr_dwn 75