1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <nevis.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* Hardware handled coherency */ 15*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 16*91f16700Schasinglulu#error "Nevis must be compiled with HW_ASSISTED_COHERENCY enabled" 17*91f16700Schasinglulu#endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 64-bit only core */ 20*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 21*91f16700Schasinglulu#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulucpu_reset_func_start nevis 25*91f16700Schasinglulu /* ---------------------------------------------------- 26*91f16700Schasinglulu * Disable speculative loads 27*91f16700Schasinglulu * ---------------------------------------------------- 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu msr SSBS, xzr 30*91f16700Schasinglulucpu_reset_func_end nevis 31*91f16700Schasinglulu 32*91f16700Schasinglulufunc nevis_core_pwr_dwn 33*91f16700Schasinglulu /* --------------------------------------------------- 34*91f16700Schasinglulu * Enable CPU power down bit in power control register 35*91f16700Schasinglulu * --------------------------------------------------- 36*91f16700Schasinglulu */ 37*91f16700Schasinglulu sysreg_bit_set NEVIS_IMP_CPUPWRCTLR_EL1, \ 38*91f16700Schasinglulu NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 39*91f16700Schasinglulu isb 40*91f16700Schasinglulu ret 41*91f16700Schasingluluendfunc nevis_core_pwr_dwn 42*91f16700Schasinglulu 43*91f16700Schasingluluerrata_report_shim nevis 44*91f16700Schasinglulu 45*91f16700Schasinglulu.section .rodata.nevis_regs, "aS" 46*91f16700Schasinglulunevis_regs: /* The ASCII list of register names to be reported */ 47*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 48*91f16700Schasinglulu 49*91f16700Schasinglulufunc nevis_cpu_reg_dump 50*91f16700Schasinglulu adr x6, nevis_regs 51*91f16700Schasinglulu mrs x8, NEVIS_CPUECTLR_EL1 52*91f16700Schasinglulu ret 53*91f16700Schasingluluendfunc nevis_cpu_reg_dump 54*91f16700Schasinglulu 55*91f16700Schasingluludeclare_cpu_ops nevis, NEVIS_MIDR, \ 56*91f16700Schasinglulu nevis_reset_func, \ 57*91f16700Schasinglulu nevis_core_pwr_dwn 58