1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <neoverse_poseidon.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu#include "wa_cve_2022_23960_bhb_vector.S" 14*91f16700Schasinglulu 15*91f16700Schasinglulu/* Hardware handled coherency */ 16*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 17*91f16700Schasinglulu#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled" 18*91f16700Schasinglulu#endif 19*91f16700Schasinglulu 20*91f16700Schasinglulu/* 64-bit only core */ 21*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 22*91f16700Schasinglulu#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23*91f16700Schasinglulu#endif 24*91f16700Schasinglulu 25*91f16700Schasinglulu#if WORKAROUND_CVE_2022_23960 26*91f16700Schasinglulu wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon 27*91f16700Schasinglulu#endif /* WORKAROUND_CVE_2022_23960 */ 28*91f16700Schasinglulu 29*91f16700Schasingluluworkaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960 30*91f16700Schasinglulu#if IMAGE_BL31 31*91f16700Schasinglulu /* 32*91f16700Schasinglulu * The Neoverse-poseidon generic vectors are overridden to apply errata 33*91f16700Schasinglulu * mitigation on exception entry from lower ELs. 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu override_vector_table wa_cve_vbar_neoverse_poseidon 36*91f16700Schasinglulu 37*91f16700Schasinglulu#endif /* IMAGE_BL31 */ 38*91f16700Schasingluluworkaround_reset_end neoverse_poseidon, CVE(2022,23960) 39*91f16700Schasinglulu 40*91f16700Schasinglulucheck_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* --------------------------------------------- 43*91f16700Schasinglulu * HW will do the cache maintenance while powering down 44*91f16700Schasinglulu * --------------------------------------------- 45*91f16700Schasinglulu */ 46*91f16700Schasinglulufunc neoverse_poseidon_core_pwr_dwn 47*91f16700Schasinglulu /* --------------------------------------------- 48*91f16700Schasinglulu * Enable CPU power down bit in power control register 49*91f16700Schasinglulu * --------------------------------------------- 50*91f16700Schasinglulu */ 51*91f16700Schasinglulu sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \ 52*91f16700Schasinglulu NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 53*91f16700Schasinglulu 54*91f16700Schasinglulu isb 55*91f16700Schasinglulu ret 56*91f16700Schasingluluendfunc neoverse_poseidon_core_pwr_dwn 57*91f16700Schasinglulu 58*91f16700Schasinglulucpu_reset_func_start neoverse_poseidon 59*91f16700Schasinglulu /* Disable speculative loads */ 60*91f16700Schasinglulu msr SSBS, xzr 61*91f16700Schasinglulucpu_reset_func_end neoverse_poseidon 62*91f16700Schasinglulu 63*91f16700Schasingluluerrata_report_shim neoverse_poseidon 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* --------------------------------------------- 66*91f16700Schasinglulu * This function provides Neoverse-Poseidon specific 67*91f16700Schasinglulu * register information for crash reporting. 68*91f16700Schasinglulu * It needs to return with x6 pointing to 69*91f16700Schasinglulu * a list of register names in ascii and 70*91f16700Schasinglulu * x8 - x15 having values of registers to be 71*91f16700Schasinglulu * reported. 72*91f16700Schasinglulu * --------------------------------------------- 73*91f16700Schasinglulu */ 74*91f16700Schasinglulu.section .rodata.neoverse_poseidon_regs, "aS" 75*91f16700Schasingluluneoverse_poseidon_regs: /* The ascii list of register names to be reported */ 76*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 77*91f16700Schasinglulu 78*91f16700Schasinglulufunc neoverse_poseidon_cpu_reg_dump 79*91f16700Schasinglulu adr x6, neoverse_poseidon_regs 80*91f16700Schasinglulu mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1 81*91f16700Schasinglulu ret 82*91f16700Schasingluluendfunc neoverse_poseidon_cpu_reg_dump 83*91f16700Schasinglulu 84*91f16700Schasingluludeclare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \ 85*91f16700Schasinglulu neoverse_poseidon_reset_func, \ 86*91f16700Schasinglulu neoverse_poseidon_core_pwr_dwn 87