1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <arch.h> 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <common/bl_common.h> 9*91f16700Schasinglulu#include <common/debug.h> 10*91f16700Schasinglulu#include <neoverse_e1.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* Hardware handled coherency */ 15*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 16*91f16700Schasinglulu#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17*91f16700Schasinglulu#endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 64-bit only core */ 20*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 21*91f16700Schasinglulu#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulu/* 25*91f16700Schasinglulu * ERRATA_DSU_936184: 26*91f16700Schasinglulu * The errata is defined in dsu_helpers.S and applies to neoverse_e1. 27*91f16700Schasinglulu * Henceforth creating symbolic names to the already existing errata 28*91f16700Schasinglulu * workaround functions to get them registered under the Errata Framework. 29*91f16700Schasinglulu */ 30*91f16700Schasinglulu.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184 31*91f16700Schasinglulu.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa 32*91f16700Schasingluluadd_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 33*91f16700Schasinglulu 34*91f16700Schasinglulucpu_reset_func_start neoverse_e1 35*91f16700Schasinglulucpu_reset_func_end neoverse_e1 36*91f16700Schasinglulu 37*91f16700Schasinglulufunc neoverse_e1_cpu_pwr_dwn 38*91f16700Schasinglulu mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 39*91f16700Schasinglulu orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 40*91f16700Schasinglulu msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 41*91f16700Schasinglulu isb 42*91f16700Schasinglulu ret 43*91f16700Schasingluluendfunc neoverse_e1_cpu_pwr_dwn 44*91f16700Schasinglulu 45*91f16700Schasingluluerrata_report_shim neoverse_e1 46*91f16700Schasinglulu 47*91f16700Schasinglulu.section .rodata.neoverse_e1_regs, "aS" 48*91f16700Schasingluluneoverse_e1_regs: /* The ascii list of register names to be reported */ 49*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 50*91f16700Schasinglulu 51*91f16700Schasinglulufunc neoverse_e1_cpu_reg_dump 52*91f16700Schasinglulu adr x6, neoverse_e1_regs 53*91f16700Schasinglulu mrs x8, NEOVERSE_E1_ECTLR_EL1 54*91f16700Schasinglulu ret 55*91f16700Schasingluluendfunc neoverse_e1_cpu_reg_dump 56*91f16700Schasinglulu 57*91f16700Schasingluludeclare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 58*91f16700Schasinglulu neoverse_e1_reset_func, \ 59*91f16700Schasinglulu neoverse_e1_cpu_pwr_dwn 60