1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <generic.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* --------------------------------------------- 15*91f16700Schasinglulu * Disable L1 data cache and unified L2 cache 16*91f16700Schasinglulu * --------------------------------------------- 17*91f16700Schasinglulu */ 18*91f16700Schasinglulufunc generic_disable_dcache 19*91f16700Schasinglulu mrs x1, sctlr_el3 20*91f16700Schasinglulu bic x1, x1, #SCTLR_C_BIT 21*91f16700Schasinglulu msr sctlr_el3, x1 22*91f16700Schasinglulu isb 23*91f16700Schasinglulu ret 24*91f16700Schasingluluendfunc generic_disable_dcache 25*91f16700Schasinglulu 26*91f16700Schasinglulufunc generic_core_pwr_dwn 27*91f16700Schasinglulu mov x18, x30 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* --------------------------------------------- 30*91f16700Schasinglulu * Turn off caches. 31*91f16700Schasinglulu * --------------------------------------------- 32*91f16700Schasinglulu */ 33*91f16700Schasinglulu bl generic_disable_dcache 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* --------------------------------------------- 36*91f16700Schasinglulu * Flush L1 caches. 37*91f16700Schasinglulu * --------------------------------------------- 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu mov x0, #DCCISW 40*91f16700Schasinglulu bl dcsw_op_level1 41*91f16700Schasinglulu 42*91f16700Schasinglulu ret x18 43*91f16700Schasingluluendfunc generic_core_pwr_dwn 44*91f16700Schasinglulu 45*91f16700Schasinglulufunc generic_cluster_pwr_dwn 46*91f16700Schasinglulu mov x18, x30 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* --------------------------------------------- 49*91f16700Schasinglulu * Turn off caches. 50*91f16700Schasinglulu * --------------------------------------------- 51*91f16700Schasinglulu */ 52*91f16700Schasinglulu bl generic_disable_dcache 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* --------------------------------------------- 55*91f16700Schasinglulu * Flush L1 caches. 56*91f16700Schasinglulu * --------------------------------------------- 57*91f16700Schasinglulu */ 58*91f16700Schasinglulu mov x0, #DCCISW 59*91f16700Schasinglulu bl dcsw_op_level1 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* --------------------------------------------- 62*91f16700Schasinglulu * Disable the optional ACP. 63*91f16700Schasinglulu * --------------------------------------------- 64*91f16700Schasinglulu */ 65*91f16700Schasinglulu bl plat_disable_acp 66*91f16700Schasinglulu 67*91f16700Schasinglulu /* --------------------------------------------- 68*91f16700Schasinglulu * Flush L2 caches. 69*91f16700Schasinglulu * --------------------------------------------- 70*91f16700Schasinglulu */ 71*91f16700Schasinglulu mov x0, #DCCISW 72*91f16700Schasinglulu bl dcsw_op_level2 73*91f16700Schasinglulu 74*91f16700Schasinglulu ret x18 75*91f16700Schasinglulu 76*91f16700Schasingluluendfunc generic_cluster_pwr_dwn 77*91f16700Schasinglulu 78*91f16700Schasinglulu/* --------------------------------------------- 79*91f16700Schasinglulu * Unimplemented functions. 80*91f16700Schasinglulu * --------------------------------------------- 81*91f16700Schasinglulu */ 82*91f16700Schasinglulu.equ generic_errata_report, 0 83*91f16700Schasinglulu.equ generic_cpu_reg_dump, 0 84*91f16700Schasinglulu.equ generic_reset_func, 0 85*91f16700Schasinglulu 86*91f16700Schasingluludeclare_cpu_ops generic, AARCH64_GENERIC_MIDR, \ 87*91f16700Schasinglulu generic_reset_func, \ 88*91f16700Schasinglulu generic_core_pwr_dwn, \ 89*91f16700Schasinglulu generic_cluster_pwr_dwn 90