1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <cpuamu.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl cpuamu_cnt_read 12*91f16700Schasinglulu .globl cpuamu_cnt_write 13*91f16700Schasinglulu .globl cpuamu_read_cpuamcntenset_el0 14*91f16700Schasinglulu .globl cpuamu_read_cpuamcntenclr_el0 15*91f16700Schasinglulu .globl cpuamu_write_cpuamcntenset_el0 16*91f16700Schasinglulu .globl cpuamu_write_cpuamcntenclr_el0 17*91f16700Schasinglulu 18*91f16700Schasinglulu/* 19*91f16700Schasinglulu * uint64_t cpuamu_cnt_read(unsigned int idx); 20*91f16700Schasinglulu * 21*91f16700Schasinglulu * Given `idx`, read the corresponding AMU counter 22*91f16700Schasinglulu * and return it in `x0`. 23*91f16700Schasinglulu */ 24*91f16700Schasinglulufunc cpuamu_cnt_read 25*91f16700Schasinglulu adr x1, 1f 26*91f16700Schasinglulu add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */ 27*91f16700Schasinglulu#if ENABLE_BTI 28*91f16700Schasinglulu add x1, x1, x0, lsl #2 /* + "bti j" instruction */ 29*91f16700Schasinglulu#endif 30*91f16700Schasinglulu br x1 31*91f16700Schasinglulu 32*91f16700Schasinglulu1: read CPUAMEVCNTR0_EL0 33*91f16700Schasinglulu read CPUAMEVCNTR1_EL0 34*91f16700Schasinglulu read CPUAMEVCNTR2_EL0 35*91f16700Schasinglulu read CPUAMEVCNTR3_EL0 36*91f16700Schasinglulu read CPUAMEVCNTR4_EL0 37*91f16700Schasingluluendfunc cpuamu_cnt_read 38*91f16700Schasinglulu 39*91f16700Schasinglulu/* 40*91f16700Schasinglulu * void cpuamu_cnt_write(unsigned int idx, uint64_t val); 41*91f16700Schasinglulu * 42*91f16700Schasinglulu * Given `idx`, write `val` to the corresponding AMU counter. 43*91f16700Schasinglulu */ 44*91f16700Schasinglulufunc cpuamu_cnt_write 45*91f16700Schasinglulu adr x2, 1f 46*91f16700Schasinglulu add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */ 47*91f16700Schasinglulu#if ENABLE_BTI 48*91f16700Schasinglulu add x2, x2, x0, lsl #2 /* + "bti j" instruction */ 49*91f16700Schasinglulu#endif 50*91f16700Schasinglulu br x2 51*91f16700Schasinglulu 52*91f16700Schasinglulu1: write CPUAMEVCNTR0_EL0 53*91f16700Schasinglulu write CPUAMEVCNTR1_EL0 54*91f16700Schasinglulu write CPUAMEVCNTR2_EL0 55*91f16700Schasinglulu write CPUAMEVCNTR3_EL0 56*91f16700Schasinglulu write CPUAMEVCNTR4_EL0 57*91f16700Schasingluluendfunc cpuamu_cnt_write 58*91f16700Schasinglulu 59*91f16700Schasinglulu/* 60*91f16700Schasinglulu * unsigned int cpuamu_read_cpuamcntenset_el0(void); 61*91f16700Schasinglulu * 62*91f16700Schasinglulu * Read the `CPUAMCNTENSET_EL0` CPU register and return 63*91f16700Schasinglulu * it in `x0`. 64*91f16700Schasinglulu */ 65*91f16700Schasinglulufunc cpuamu_read_cpuamcntenset_el0 66*91f16700Schasinglulu mrs x0, CPUAMCNTENSET_EL0 67*91f16700Schasinglulu ret 68*91f16700Schasingluluendfunc cpuamu_read_cpuamcntenset_el0 69*91f16700Schasinglulu 70*91f16700Schasinglulu/* 71*91f16700Schasinglulu * unsigned int cpuamu_read_cpuamcntenclr_el0(void); 72*91f16700Schasinglulu * 73*91f16700Schasinglulu * Read the `CPUAMCNTENCLR_EL0` CPU register and return 74*91f16700Schasinglulu * it in `x0`. 75*91f16700Schasinglulu */ 76*91f16700Schasinglulufunc cpuamu_read_cpuamcntenclr_el0 77*91f16700Schasinglulu mrs x0, CPUAMCNTENCLR_EL0 78*91f16700Schasinglulu ret 79*91f16700Schasingluluendfunc cpuamu_read_cpuamcntenclr_el0 80*91f16700Schasinglulu 81*91f16700Schasinglulu/* 82*91f16700Schasinglulu * void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 83*91f16700Schasinglulu * 84*91f16700Schasinglulu * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. 85*91f16700Schasinglulu */ 86*91f16700Schasinglulufunc cpuamu_write_cpuamcntenset_el0 87*91f16700Schasinglulu msr CPUAMCNTENSET_EL0, x0 88*91f16700Schasinglulu ret 89*91f16700Schasingluluendfunc cpuamu_write_cpuamcntenset_el0 90*91f16700Schasinglulu 91*91f16700Schasinglulu/* 92*91f16700Schasinglulu * void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 93*91f16700Schasinglulu * 94*91f16700Schasinglulu * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. 95*91f16700Schasinglulu */ 96*91f16700Schasinglulufunc cpuamu_write_cpuamcntenclr_el0 97*91f16700Schasinglulu msr CPUAMCNTENCLR_EL0, x0 98*91f16700Schasinglulu ret 99*91f16700Schasingluluendfunc cpuamu_write_cpuamcntenclr_el0 100