1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, Google LLC. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <cortex_x1.h> 9*91f16700Schasinglulu#include <cpu_macros.S> 10*91f16700Schasinglulu#include "wa_cve_2022_23960_bhb_vector.S" 11*91f16700Schasinglulu 12*91f16700Schasinglulu/* Hardware handled coherency */ 13*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 14*91f16700Schasinglulu#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled" 15*91f16700Schasinglulu#endif 16*91f16700Schasinglulu 17*91f16700Schasinglulu/* 64-bit only core */ 18*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 19*91f16700Schasinglulu#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20*91f16700Schasinglulu#endif 21*91f16700Schasinglulu 22*91f16700Schasinglulu#if WORKAROUND_CVE_2022_23960 23*91f16700Schasinglulu wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1 24*91f16700Schasinglulu#endif /* WORKAROUND_CVE_2022_23960 */ 25*91f16700Schasinglulu 26*91f16700Schasingluluworkaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305 27*91f16700Schasinglulu sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1) 28*91f16700Schasingluluworkaround_reset_end cortex_x1, ERRATUM(1688305) 29*91f16700Schasinglulu 30*91f16700Schasinglulucheck_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0) 31*91f16700Schasinglulu 32*91f16700Schasingluluworkaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534 33*91f16700Schasinglulu sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2) 34*91f16700Schasingluluworkaround_reset_end cortex_x1, ERRATUM(1821534) 35*91f16700Schasinglulu 36*91f16700Schasinglulucheck_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0) 37*91f16700Schasinglulu 38*91f16700Schasingluluworkaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429 39*91f16700Schasinglulu sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53) 40*91f16700Schasingluluworkaround_reset_end cortex_x1, ERRATUM(1827429) 41*91f16700Schasinglulu 42*91f16700Schasinglulucheck_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0) 43*91f16700Schasinglulu 44*91f16700Schasinglulucheck_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 45*91f16700Schasinglulu 46*91f16700Schasingluluworkaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 47*91f16700Schasinglulu#if IMAGE_BL31 48*91f16700Schasinglulu /* 49*91f16700Schasinglulu * The Cortex-X1 generic vectors are overridden to apply errata 50*91f16700Schasinglulu * mitigation on exception entry from lower ELs. 51*91f16700Schasinglulu */ 52*91f16700Schasinglulu override_vector_table wa_cve_vbar_cortex_x1 53*91f16700Schasinglulu#endif /* IMAGE_BL31 */ 54*91f16700Schasingluluworkaround_reset_end cortex_x1, CVE(2022, 23960) 55*91f16700Schasinglulu 56*91f16700Schasinglulucpu_reset_func_start cortex_x1 57*91f16700Schasinglulucpu_reset_func_end cortex_x1 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* --------------------------------------------- 60*91f16700Schasinglulu * HW will do the cache maintenance while powering down 61*91f16700Schasinglulu * --------------------------------------------- 62*91f16700Schasinglulu */ 63*91f16700Schasinglulufunc cortex_x1_core_pwr_dwn 64*91f16700Schasinglulu sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK 65*91f16700Schasinglulu isb 66*91f16700Schasinglulu ret 67*91f16700Schasingluluendfunc cortex_x1_core_pwr_dwn 68*91f16700Schasinglulu 69*91f16700Schasingluluerrata_report_shim cortex_x1 70*91f16700Schasinglulu 71*91f16700Schasinglulu /* --------------------------------------------- 72*91f16700Schasinglulu * This function provides Cortex X1 specific 73*91f16700Schasinglulu * register information for crash reporting. 74*91f16700Schasinglulu * It needs to return with x6 pointing to 75*91f16700Schasinglulu * a list of register names in ascii and 76*91f16700Schasinglulu * x8 - x15 having values of registers to be 77*91f16700Schasinglulu * reported. 78*91f16700Schasinglulu * --------------------------------------------- 79*91f16700Schasinglulu */ 80*91f16700Schasinglulu.section .rodata.cortex_x1_regs, "aS" 81*91f16700Schasinglulucortex_x1_regs: /* The ascii list of register names to be reported */ 82*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 83*91f16700Schasinglulu 84*91f16700Schasinglulufunc cortex_x1_cpu_reg_dump 85*91f16700Schasinglulu adr x6, cortex_x1_regs 86*91f16700Schasinglulu mrs x8, CORTEX_X1_CPUECTLR_EL1 87*91f16700Schasinglulu ret 88*91f16700Schasingluluendfunc cortex_x1_cpu_reg_dump 89*91f16700Schasinglulu 90*91f16700Schasingluludeclare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \ 91*91f16700Schasinglulu cortex_x1_reset_func, \ 92*91f16700Schasinglulu cortex_x1_core_pwr_dwn 93