1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <cortex_gelas.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* Hardware handled coherency */ 15*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 16*91f16700Schasinglulu#error "Gelas must be compiled with HW_ASSISTED_COHERENCY enabled" 17*91f16700Schasinglulu#endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 64-bit only core */ 20*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 21*91f16700Schasinglulu#error "Gelas supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulucpu_reset_func_start cortex_gelas 25*91f16700Schasinglulu /* ---------------------------------------------------- 26*91f16700Schasinglulu * Disable speculative loads 27*91f16700Schasinglulu * ---------------------------------------------------- 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu msr SSBS, xzr 30*91f16700Schasinglulucpu_reset_func_end cortex_gelas 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* ---------------------------------------------------- 33*91f16700Schasinglulu * HW will do the cache maintenance while powering down 34*91f16700Schasinglulu * ---------------------------------------------------- 35*91f16700Schasinglulu */ 36*91f16700Schasinglulufunc cortex_gelas_core_pwr_dwn 37*91f16700Schasinglulu#if ENABLE_SME_FOR_NS 38*91f16700Schasinglulu /* --------------------------------------------------- 39*91f16700Schasinglulu * Disable SME if enabled and supported 40*91f16700Schasinglulu * --------------------------------------------------- 41*91f16700Schasinglulu */ 42*91f16700Schasinglulu mrs x0, ID_AA64PFR1_EL1 43*91f16700Schasinglulu ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \ 44*91f16700Schasinglulu #ID_AA64PFR1_EL1_SME_WIDTH 45*91f16700Schasinglulu cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED 46*91f16700Schasinglulu b.eq 1f 47*91f16700Schasinglulu msr CORTEX_GELAS_SVCRSM, xzr 48*91f16700Schasinglulu msr CORTEX_GELAS_SVCRZA, xzr 49*91f16700Schasinglulu1: 50*91f16700Schasinglulu#endif 51*91f16700Schasinglulu /* --------------------------------------------------- 52*91f16700Schasinglulu * Enable CPU power down bit in power control register 53*91f16700Schasinglulu * --------------------------------------------------- 54*91f16700Schasinglulu */ 55*91f16700Schasinglulu sysreg_bit_set CORTEX_GELAS_CPUPWRCTLR_EL1, \ 56*91f16700Schasinglulu CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 57*91f16700Schasinglulu isb 58*91f16700Schasinglulu ret 59*91f16700Schasingluluendfunc cortex_gelas_core_pwr_dwn 60*91f16700Schasinglulu 61*91f16700Schasingluluerrata_report_shim cortex_gelas 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* --------------------------------------------- 64*91f16700Schasinglulu * This function provides Gelas specific 65*91f16700Schasinglulu * register information for crash reporting. 66*91f16700Schasinglulu * It needs to return with x6 pointing to 67*91f16700Schasinglulu * a list of register names in ascii and 68*91f16700Schasinglulu * x8 - x15 having values of registers to be 69*91f16700Schasinglulu * reported. 70*91f16700Schasinglulu * --------------------------------------------- 71*91f16700Schasinglulu */ 72*91f16700Schasinglulu.section .rodata.cortex_gelas_regs, "aS" 73*91f16700Schasinglulucortex_gelas_regs: /* The ASCII list of register names to be reported */ 74*91f16700Schasinglulu .asciz "imp_cpuectlr_el1", "" 75*91f16700Schasinglulu 76*91f16700Schasinglulufunc cortex_gelas_cpu_reg_dump 77*91f16700Schasinglulu adr x6, cortex_gelas_regs 78*91f16700Schasinglulu mrs x8, CORTEX_GELAS_IMP_CPUECTLR_EL1 79*91f16700Schasinglulu ret 80*91f16700Schasingluluendfunc cortex_gelas_cpu_reg_dump 81*91f16700Schasinglulu 82*91f16700Schasingluludeclare_cpu_ops cortex_gelas, CORTEX_GELAS_MIDR, \ 83*91f16700Schasinglulu cortex_gelas_reset_func, \ 84*91f16700Schasinglulu cortex_gelas_core_pwr_dwn 85