1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <cortex_a76ae.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include "wa_cve_2022_23960_bhb_vector.S" 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* Hardware handled coherency */ 15*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 16*91f16700Schasinglulu#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17*91f16700Schasinglulu#endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 64-bit only core */ 20*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 21*91f16700Schasinglulu#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulu#if WORKAROUND_CVE_2022_23960 25*91f16700Schasinglulu wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae 26*91f16700Schasinglulu#endif /* WORKAROUND_CVE_2022_23960 */ 27*91f16700Schasinglulu 28*91f16700Schasinglulucheck_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 29*91f16700Schasinglulu 30*91f16700Schasingluluworkaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 31*91f16700Schasinglulu#if IMAGE_BL31 32*91f16700Schasinglulu /* 33*91f16700Schasinglulu * The Cortex-A76ae generic vectors are overridden to apply errata 34*91f16700Schasinglulu * mitigation on exception entry from lower ELs. 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu override_vector_table wa_cve_vbar_cortex_a76ae 37*91f16700Schasinglulu isb 38*91f16700Schasinglulu#endif /* IMAGE_BL31 */ 39*91f16700Schasingluluworkaround_reset_end cortex_a76ae, CVE(2022, 23960) 40*91f16700Schasinglulu 41*91f16700Schasinglulucpu_reset_func_start cortex_a76ae 42*91f16700Schasinglulucpu_reset_func_end cortex_a76ae 43*91f16700Schasinglulu 44*91f16700Schasingluluerrata_report_shim cortex_a76ae 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* ---------------------------------------------------- 47*91f16700Schasinglulu * HW will do the cache maintenance while powering down 48*91f16700Schasinglulu * ---------------------------------------------------- 49*91f16700Schasinglulu */ 50*91f16700Schasinglulufunc cortex_a76ae_core_pwr_dwn 51*91f16700Schasinglulu sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK 52*91f16700Schasinglulu isb 53*91f16700Schasinglulu ret 54*91f16700Schasingluluendfunc cortex_a76ae_core_pwr_dwn 55*91f16700Schasinglulu 56*91f16700Schasinglulu /* --------------------------------------------- 57*91f16700Schasinglulu * This function provides cortex_a76ae specific 58*91f16700Schasinglulu * register information for crash reporting. 59*91f16700Schasinglulu * It needs to return with x6 pointing to 60*91f16700Schasinglulu * a list of register names in ascii and 61*91f16700Schasinglulu * x8 - x15 having values of registers to be 62*91f16700Schasinglulu * reported. 63*91f16700Schasinglulu * --------------------------------------------- 64*91f16700Schasinglulu */ 65*91f16700Schasinglulu.section .rodata.cortex_a76ae_regs, "aS" 66*91f16700Schasinglulucortex_a76ae_regs: /* The ASCII list of register names to be reported */ 67*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 68*91f16700Schasinglulu 69*91f16700Schasinglulufunc cortex_a76ae_cpu_reg_dump 70*91f16700Schasinglulu adr x6, cortex_a76ae_regs 71*91f16700Schasinglulu mrs x8, CORTEX_A76AE_CPUECTLR_EL1 72*91f16700Schasinglulu ret 73*91f16700Schasingluluendfunc cortex_a76ae_cpu_reg_dump 74*91f16700Schasinglulu 75*91f16700Schasingluludeclare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ 76*91f16700Schasinglulu cortex_a76ae_core_pwr_dwn 77