xref: /arm-trusted-firmware/lib/cpus/aarch64/cortex_a75_pubsub.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #include <cortex_a75.h>
8*91f16700Schasinglulu #include <cpuamu.h>
9*91f16700Schasinglulu #include <lib/el3_runtime/pubsub_events.h>
10*91f16700Schasinglulu 
11*91f16700Schasinglulu static void *cortex_a75_context_save(const void *arg)
12*91f16700Schasinglulu {
13*91f16700Schasinglulu 	if (midr_match(CORTEX_A75_MIDR) != 0)
14*91f16700Schasinglulu 		cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
15*91f16700Schasinglulu 
16*91f16700Schasinglulu 	return (void *)0;
17*91f16700Schasinglulu }
18*91f16700Schasinglulu 
19*91f16700Schasinglulu static void *cortex_a75_context_restore(const void *arg)
20*91f16700Schasinglulu {
21*91f16700Schasinglulu 	if (midr_match(CORTEX_A75_MIDR) != 0)
22*91f16700Schasinglulu 		cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
23*91f16700Schasinglulu 
24*91f16700Schasinglulu 	return (void *)0;
25*91f16700Schasinglulu }
26*91f16700Schasinglulu 
27*91f16700Schasinglulu SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_a75_context_save);
28*91f16700Schasinglulu SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, cortex_a75_context_restore);
29