1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <arch.h> 7*91f16700Schasinglulu 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <common/debug.h> 11*91f16700Schasinglulu#include <cortex_a65ae.h> 12*91f16700Schasinglulu#include <cpu_macros.S> 13*91f16700Schasinglulu#include <plat_macros.S> 14*91f16700Schasinglulu 15*91f16700Schasinglulu/* Hardware handled coherency */ 16*91f16700Schasinglulu#if !HW_ASSISTED_COHERENCY 17*91f16700Schasinglulu#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled" 18*91f16700Schasinglulu#endif 19*91f16700Schasinglulu 20*91f16700Schasinglulu/* 64-bit only core */ 21*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS 22*91f16700Schasinglulu#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23*91f16700Schasinglulu#endif 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* 26*91f16700Schasinglulu * ERRATA_DSU_936184 : 27*91f16700Schasinglulu * The errata is defined in dsu_helpers.S but applies to cortex_a65ae 28*91f16700Schasinglulu * as well. Henceforth creating symbolic names to the already existing errata 29*91f16700Schasinglulu * workaround functions to get them registered under the Errata Framework. 30*91f16700Schasinglulu */ 31*91f16700Schasinglulu.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184 32*91f16700Schasinglulu.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa 33*91f16700Schasingluluadd_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 34*91f16700Schasinglulu 35*91f16700Schasinglulucpu_reset_func_start cortex_a65ae 36*91f16700Schasinglulucpu_reset_func_end cortex_a65ae 37*91f16700Schasinglulu 38*91f16700Schasinglulufunc cortex_a65ae_cpu_pwr_dwn 39*91f16700Schasinglulu sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 40*91f16700Schasinglulu isb 41*91f16700Schasinglulu ret 42*91f16700Schasingluluendfunc cortex_a65ae_cpu_pwr_dwn 43*91f16700Schasinglulu 44*91f16700Schasingluluerrata_report_shim cortex_a65ae 45*91f16700Schasinglulu 46*91f16700Schasinglulu.section .rodata.cortex_a65ae_regs, "aS" 47*91f16700Schasinglulucortex_a65ae_regs: /* The ascii list of register names to be reported */ 48*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 49*91f16700Schasinglulu 50*91f16700Schasinglulufunc cortex_a65ae_cpu_reg_dump 51*91f16700Schasinglulu adr x6, cortex_a65ae_regs 52*91f16700Schasinglulu mrs x8, CORTEX_A65AE_ECTLR_EL1 53*91f16700Schasinglulu ret 54*91f16700Schasingluluendfunc cortex_a65ae_cpu_reg_dump 55*91f16700Schasinglulu 56*91f16700Schasingluludeclare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \ 57*91f16700Schasinglulu cortex_a65ae_reset_func, \ 58*91f16700Schasinglulu cortex_a65ae_cpu_pwr_dwn 59