1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2019, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <arch.h> 7*91f16700Schasinglulu 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <common/debug.h> 11*91f16700Schasinglulu#include <cortex_a65.h> 12*91f16700Schasinglulu#include <cpu_macros.S> 13*91f16700Schasinglulu#include <plat_macros.S> 14*91f16700Schasinglulu 15*91f16700Schasinglulu/* Hardware handled coherency */ 16*91f16700Schasinglulu#if !HW_ASSISTED_COHERENCY 17*91f16700Schasinglulu#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled" 18*91f16700Schasinglulu#endif 19*91f16700Schasinglulu 20*91f16700Schasinglulu/* 64-bit only core */ 21*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS 22*91f16700Schasinglulu#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23*91f16700Schasinglulu#endif 24*91f16700Schasinglulu 25*91f16700Schasinglulu/* ------------------------------------------------- 26*91f16700Schasinglulu * The CPU Ops reset function for Cortex-A65. 27*91f16700Schasinglulu * Shall clobber: x0-x19 28*91f16700Schasinglulu * ------------------------------------------------- 29*91f16700Schasinglulu */ 30*91f16700Schasinglulufunc cortex_a65_reset_func 31*91f16700Schasinglulu mov x19, x30 32*91f16700Schasinglulu 33*91f16700Schasinglulu#if ERRATA_DSU_936184 34*91f16700Schasinglulu bl errata_dsu_936184_wa 35*91f16700Schasinglulu#endif 36*91f16700Schasinglulu 37*91f16700Schasinglulu ret x19 38*91f16700Schasingluluendfunc cortex_a65_reset_func 39*91f16700Schasinglulu 40*91f16700Schasinglulufunc cortex_a65_cpu_pwr_dwn 41*91f16700Schasinglulu mrs x0, CORTEX_A65_CPUPWRCTLR_EL1 42*91f16700Schasinglulu orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 43*91f16700Schasinglulu msr CORTEX_A65_CPUPWRCTLR_EL1, x0 44*91f16700Schasinglulu isb 45*91f16700Schasinglulu ret 46*91f16700Schasingluluendfunc cortex_a65_cpu_pwr_dwn 47*91f16700Schasinglulu 48*91f16700Schasinglulu#if REPORT_ERRATA 49*91f16700Schasinglulu/* 50*91f16700Schasinglulu * Errata printing function for Cortex-A65. Must follow AAPCS. 51*91f16700Schasinglulu */ 52*91f16700Schasinglulufunc cortex_a65_errata_report 53*91f16700Schasinglulu stp x8, x30, [sp, #-16]! 54*91f16700Schasinglulu 55*91f16700Schasinglulu bl cpu_get_rev_var 56*91f16700Schasinglulu mov x8, x0 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* 59*91f16700Schasinglulu * Report all errata. The revision-variant information is passed to 60*91f16700Schasinglulu * checking functions of each errata. 61*91f16700Schasinglulu */ 62*91f16700Schasinglulu report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184 63*91f16700Schasinglulu 64*91f16700Schasinglulu ldp x8, x30, [sp], #16 65*91f16700Schasinglulu ret 66*91f16700Schasingluluendfunc cortex_a65_errata_report 67*91f16700Schasinglulu#endif 68*91f16700Schasinglulu 69*91f16700Schasinglulu.section .rodata.cortex_a65_regs, "aS" 70*91f16700Schasinglulucortex_a65_regs: /* The ascii list of register names to be reported */ 71*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 72*91f16700Schasinglulu 73*91f16700Schasinglulufunc cortex_a65_cpu_reg_dump 74*91f16700Schasinglulu adr x6, cortex_a65_regs 75*91f16700Schasinglulu mrs x8, CORTEX_A65_ECTLR_EL1 76*91f16700Schasinglulu ret 77*91f16700Schasingluluendfunc cortex_a65_cpu_reg_dump 78*91f16700Schasinglulu 79*91f16700Schasingluludeclare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \ 80*91f16700Schasinglulu cortex_a65_reset_func, \ 81*91f16700Schasinglulu cortex_a65_cpu_pwr_dwn 82