1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <cortex_a520.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* Hardware handled coherency */ 15*91f16700Schasinglulu#if HW_ASSISTED_COHERENCY == 0 16*91f16700Schasinglulu#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 17*91f16700Schasinglulu#endif 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 64-bit only core */ 20*91f16700Schasinglulu#if CTX_INCLUDE_AARCH32_REGS == 1 21*91f16700Schasinglulu#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* ---------------------------------------------------- 25*91f16700Schasinglulu * HW will do the cache maintenance while powering down 26*91f16700Schasinglulu * ---------------------------------------------------- 27*91f16700Schasinglulu */ 28*91f16700Schasinglulufunc cortex_a520_core_pwr_dwn 29*91f16700Schasinglulu /* --------------------------------------------------- 30*91f16700Schasinglulu * Enable CPU power down bit in power control register 31*91f16700Schasinglulu * --------------------------------------------------- 32*91f16700Schasinglulu */ 33*91f16700Schasinglulu sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 34*91f16700Schasinglulu isb 35*91f16700Schasinglulu ret 36*91f16700Schasingluluendfunc cortex_a520_core_pwr_dwn 37*91f16700Schasinglulu 38*91f16700Schasingluluerrata_report_shim cortex_a520 39*91f16700Schasinglulu 40*91f16700Schasinglulucpu_reset_func_start cortex_a520 41*91f16700Schasinglulu /* Disable speculative loads */ 42*91f16700Schasinglulu msr SSBS, xzr 43*91f16700Schasinglulucpu_reset_func_end cortex_a520 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* --------------------------------------------- 46*91f16700Schasinglulu * This function provides Cortex A520 specific 47*91f16700Schasinglulu * register information for crash reporting. 48*91f16700Schasinglulu * It needs to return with x6 pointing to 49*91f16700Schasinglulu * a list of register names in ascii and 50*91f16700Schasinglulu * x8 - x15 having values of registers to be 51*91f16700Schasinglulu * reported. 52*91f16700Schasinglulu * --------------------------------------------- 53*91f16700Schasinglulu */ 54*91f16700Schasinglulu.section .rodata.cortex_a520_regs, "aS" 55*91f16700Schasinglulucortex_a520_regs: /* The ascii list of register names to be reported */ 56*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 57*91f16700Schasinglulu 58*91f16700Schasinglulufunc cortex_a520_cpu_reg_dump 59*91f16700Schasinglulu adr x6, cortex_a520_regs 60*91f16700Schasinglulu mrs x8, CORTEX_A520_CPUECTLR_EL1 61*91f16700Schasinglulu ret 62*91f16700Schasingluluendfunc cortex_a520_cpu_reg_dump 63*91f16700Schasinglulu 64*91f16700Schasingluludeclare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 65*91f16700Schasinglulu cortex_a520_reset_func, \ 66*91f16700Schasinglulu cortex_a520_core_pwr_dwn 67