1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <cortex_a35.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu#include <plat_macros.S> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* --------------------------------------------- 15*91f16700Schasinglulu * Disable L1 data cache and unified L2 cache 16*91f16700Schasinglulu * --------------------------------------------- 17*91f16700Schasinglulu */ 18*91f16700Schasinglulufunc cortex_a35_disable_dcache 19*91f16700Schasinglulu sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 20*91f16700Schasinglulu isb 21*91f16700Schasinglulu ret 22*91f16700Schasingluluendfunc cortex_a35_disable_dcache 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* --------------------------------------------- 25*91f16700Schasinglulu * Disable intra-cluster coherency 26*91f16700Schasinglulu * --------------------------------------------- 27*91f16700Schasinglulu */ 28*91f16700Schasinglulufunc cortex_a35_disable_smp 29*91f16700Schasinglulu sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 30*91f16700Schasinglulu isb 31*91f16700Schasinglulu dsb sy 32*91f16700Schasinglulu ret 33*91f16700Schasingluluendfunc cortex_a35_disable_smp 34*91f16700Schasinglulu 35*91f16700Schasingluluworkaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 36*91f16700Schasinglulu sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI 37*91f16700Schasingluluworkaround_reset_end cortex_a35, ERRATUM(855472) 38*91f16700Schasinglulu 39*91f16700Schasinglulucheck_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) 40*91f16700Schasinglulu 41*91f16700Schasinglulu /* ------------------------------------------------- 42*91f16700Schasinglulu * The CPU Ops reset function for Cortex-A35. 43*91f16700Schasinglulu * ------------------------------------------------- 44*91f16700Schasinglulu */ 45*91f16700Schasinglulucpu_reset_func_start cortex_a35 46*91f16700Schasinglulu /* --------------------------------------------- 47*91f16700Schasinglulu * Enable the SMP bit. 48*91f16700Schasinglulu * --------------------------------------------- 49*91f16700Schasinglulu */ 50*91f16700Schasinglulu sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 51*91f16700Schasinglulucpu_reset_func_end cortex_a35 52*91f16700Schasinglulu 53*91f16700Schasinglulufunc cortex_a35_core_pwr_dwn 54*91f16700Schasinglulu mov x18, x30 55*91f16700Schasinglulu 56*91f16700Schasinglulu /* --------------------------------------------- 57*91f16700Schasinglulu * Turn off caches. 58*91f16700Schasinglulu * --------------------------------------------- 59*91f16700Schasinglulu */ 60*91f16700Schasinglulu bl cortex_a35_disable_dcache 61*91f16700Schasinglulu 62*91f16700Schasinglulu /* --------------------------------------------- 63*91f16700Schasinglulu * Flush L1 caches. 64*91f16700Schasinglulu * --------------------------------------------- 65*91f16700Schasinglulu */ 66*91f16700Schasinglulu mov x0, #DCCISW 67*91f16700Schasinglulu bl dcsw_op_level1 68*91f16700Schasinglulu 69*91f16700Schasinglulu /* --------------------------------------------- 70*91f16700Schasinglulu * Come out of intra cluster coherency 71*91f16700Schasinglulu * --------------------------------------------- 72*91f16700Schasinglulu */ 73*91f16700Schasinglulu mov x30, x18 74*91f16700Schasinglulu b cortex_a35_disable_smp 75*91f16700Schasingluluendfunc cortex_a35_core_pwr_dwn 76*91f16700Schasinglulu 77*91f16700Schasinglulufunc cortex_a35_cluster_pwr_dwn 78*91f16700Schasinglulu mov x18, x30 79*91f16700Schasinglulu 80*91f16700Schasinglulu /* --------------------------------------------- 81*91f16700Schasinglulu * Turn off caches. 82*91f16700Schasinglulu * --------------------------------------------- 83*91f16700Schasinglulu */ 84*91f16700Schasinglulu bl cortex_a35_disable_dcache 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* --------------------------------------------- 87*91f16700Schasinglulu * Flush L1 caches. 88*91f16700Schasinglulu * --------------------------------------------- 89*91f16700Schasinglulu */ 90*91f16700Schasinglulu mov x0, #DCCISW 91*91f16700Schasinglulu bl dcsw_op_level1 92*91f16700Schasinglulu 93*91f16700Schasinglulu /* --------------------------------------------- 94*91f16700Schasinglulu * Disable the optional ACP. 95*91f16700Schasinglulu * --------------------------------------------- 96*91f16700Schasinglulu */ 97*91f16700Schasinglulu bl plat_disable_acp 98*91f16700Schasinglulu 99*91f16700Schasinglulu /* --------------------------------------------- 100*91f16700Schasinglulu * Flush L2 caches. 101*91f16700Schasinglulu * --------------------------------------------- 102*91f16700Schasinglulu */ 103*91f16700Schasinglulu mov x0, #DCCISW 104*91f16700Schasinglulu bl dcsw_op_level2 105*91f16700Schasinglulu 106*91f16700Schasinglulu /* --------------------------------------------- 107*91f16700Schasinglulu * Come out of intra cluster coherency 108*91f16700Schasinglulu * --------------------------------------------- 109*91f16700Schasinglulu */ 110*91f16700Schasinglulu mov x30, x18 111*91f16700Schasinglulu b cortex_a35_disable_smp 112*91f16700Schasingluluendfunc cortex_a35_cluster_pwr_dwn 113*91f16700Schasinglulu 114*91f16700Schasingluluerrata_report_shim cortex_a35 115*91f16700Schasinglulu 116*91f16700Schasinglulu /* --------------------------------------------- 117*91f16700Schasinglulu * This function provides cortex_a35 specific 118*91f16700Schasinglulu * register information for crash reporting. 119*91f16700Schasinglulu * It needs to return with x6 pointing to 120*91f16700Schasinglulu * a list of register names in ascii and 121*91f16700Schasinglulu * x8 - x15 having values of registers to be 122*91f16700Schasinglulu * reported. 123*91f16700Schasinglulu * --------------------------------------------- 124*91f16700Schasinglulu */ 125*91f16700Schasinglulu.section .rodata.cortex_a35_regs, "aS" 126*91f16700Schasinglulucortex_a35_regs: /* The ascii list of register names to be reported */ 127*91f16700Schasinglulu .asciz "cpuectlr_el1", "" 128*91f16700Schasinglulu 129*91f16700Schasinglulufunc cortex_a35_cpu_reg_dump 130*91f16700Schasinglulu adr x6, cortex_a35_regs 131*91f16700Schasinglulu mrs x8, CORTEX_A35_CPUECTLR_EL1 132*91f16700Schasinglulu ret 133*91f16700Schasingluluendfunc cortex_a35_cpu_reg_dump 134*91f16700Schasinglulu 135*91f16700Schasingluludeclare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ 136*91f16700Schasinglulu cortex_a35_reset_func, \ 137*91f16700Schasinglulu cortex_a35_core_pwr_dwn, \ 138*91f16700Schasinglulu cortex_a35_cluster_pwr_dwn 139