1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <aem_generic.h> 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <cpu_macros.S> 10*91f16700Schasinglulu 11*91f16700Schasinglulufunc aem_generic_core_pwr_dwn 12*91f16700Schasinglulu /* --------------------------------------------- 13*91f16700Schasinglulu * Disable the Data Cache. 14*91f16700Schasinglulu * --------------------------------------------- 15*91f16700Schasinglulu */ 16*91f16700Schasinglulu mrs x1, sctlr_el3 17*91f16700Schasinglulu bic x1, x1, #SCTLR_C_BIT 18*91f16700Schasinglulu msr sctlr_el3, x1 19*91f16700Schasinglulu isb 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* --------------------------------------------- 22*91f16700Schasinglulu * AEM model supports L3 caches in which case L2 23*91f16700Schasinglulu * will be private per core caches and flush 24*91f16700Schasinglulu * from L1 to L2 is not sufficient. 25*91f16700Schasinglulu * --------------------------------------------- 26*91f16700Schasinglulu */ 27*91f16700Schasinglulu mrs x1, clidr_el1 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* --------------------------------------------- 30*91f16700Schasinglulu * Check if L3 cache is implemented. 31*91f16700Schasinglulu * --------------------------------------------- 32*91f16700Schasinglulu */ 33*91f16700Schasinglulu tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* --------------------------------------------- 36*91f16700Schasinglulu * There is no L3 cache, flush L1 to L2 only. 37*91f16700Schasinglulu * --------------------------------------------- 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu mov x0, #DCCISW 40*91f16700Schasinglulu b.eq dcsw_op_level1 41*91f16700Schasinglulu 42*91f16700Schasinglulu mov x18, x30 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* --------------------------------------------- 45*91f16700Schasinglulu * Flush L1 cache to L2. 46*91f16700Schasinglulu * --------------------------------------------- 47*91f16700Schasinglulu */ 48*91f16700Schasinglulu bl dcsw_op_level1 49*91f16700Schasinglulu mov x30, x18 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* --------------------------------------------- 52*91f16700Schasinglulu * Flush L2 cache to L3. 53*91f16700Schasinglulu * --------------------------------------------- 54*91f16700Schasinglulu */ 55*91f16700Schasinglulu mov x0, #DCCISW 56*91f16700Schasinglulu b dcsw_op_level2 57*91f16700Schasingluluendfunc aem_generic_core_pwr_dwn 58*91f16700Schasinglulu 59*91f16700Schasinglulufunc aem_generic_cluster_pwr_dwn 60*91f16700Schasinglulu /* --------------------------------------------- 61*91f16700Schasinglulu * Disable the Data Cache. 62*91f16700Schasinglulu * --------------------------------------------- 63*91f16700Schasinglulu */ 64*91f16700Schasinglulu mrs x1, sctlr_el3 65*91f16700Schasinglulu bic x1, x1, #SCTLR_C_BIT 66*91f16700Schasinglulu msr sctlr_el3, x1 67*91f16700Schasinglulu isb 68*91f16700Schasinglulu 69*91f16700Schasinglulu /* --------------------------------------------- 70*91f16700Schasinglulu * Flush all caches to PoC. 71*91f16700Schasinglulu * --------------------------------------------- 72*91f16700Schasinglulu */ 73*91f16700Schasinglulu mov x0, #DCCISW 74*91f16700Schasinglulu b dcsw_op_all 75*91f16700Schasingluluendfunc aem_generic_cluster_pwr_dwn 76*91f16700Schasinglulu 77*91f16700Schasinglulu#if REPORT_ERRATA 78*91f16700Schasinglulu/* 79*91f16700Schasinglulu * Errata printing function for AEM. Must follow AAPCS. 80*91f16700Schasinglulu */ 81*91f16700Schasinglulufunc aem_generic_errata_report 82*91f16700Schasinglulu ret 83*91f16700Schasingluluendfunc aem_generic_errata_report 84*91f16700Schasinglulu#endif 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* --------------------------------------------- 87*91f16700Schasinglulu * This function provides cpu specific 88*91f16700Schasinglulu * register information for crash reporting. 89*91f16700Schasinglulu * It needs to return with x6 pointing to 90*91f16700Schasinglulu * a list of register names in ascii and 91*91f16700Schasinglulu * x8 - x15 having values of registers to be 92*91f16700Schasinglulu * reported. 93*91f16700Schasinglulu * --------------------------------------------- 94*91f16700Schasinglulu */ 95*91f16700Schasinglulu.section .rodata.aem_generic_regs, "aS" 96*91f16700Schasingluluaem_generic_regs: /* The ascii list of register names to be reported */ 97*91f16700Schasinglulu .asciz "" /* no registers to report */ 98*91f16700Schasinglulu 99*91f16700Schasinglulufunc aem_generic_cpu_reg_dump 100*91f16700Schasinglulu adr x6, aem_generic_regs 101*91f16700Schasinglulu ret 102*91f16700Schasingluluendfunc aem_generic_cpu_reg_dump 103*91f16700Schasinglulu 104*91f16700Schasinglulu 105*91f16700Schasinglulu/* cpu_ops for Base AEM FVP */ 106*91f16700Schasingluludeclare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ 107*91f16700Schasinglulu aem_generic_core_pwr_dwn, \ 108*91f16700Schasinglulu aem_generic_cluster_pwr_dwn 109*91f16700Schasinglulu 110*91f16700Schasinglulu/* cpu_ops for Foundation FVP */ 111*91f16700Schasingluludeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \ 112*91f16700Schasinglulu aem_generic_core_pwr_dwn, \ 113*91f16700Schasinglulu aem_generic_cluster_pwr_dwn 114