1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <assert_macros.S> 10*91f16700Schasinglulu#include <cortex_a5.h> 11*91f16700Schasinglulu#include <cpu_macros.S> 12*91f16700Schasinglulu 13*91f16700Schasinglulu .macro assert_cache_enabled 14*91f16700Schasinglulu#if ENABLE_ASSERTIONS 15*91f16700Schasinglulu ldcopr r0, SCTLR 16*91f16700Schasinglulu tst r0, #SCTLR_C_BIT 17*91f16700Schasinglulu ASM_ASSERT(eq) 18*91f16700Schasinglulu#endif 19*91f16700Schasinglulu .endm 20*91f16700Schasinglulu 21*91f16700Schasinglulufunc cortex_a5_disable_smp 22*91f16700Schasinglulu ldcopr r0, ACTLR 23*91f16700Schasinglulu bic r0, #CORTEX_A5_ACTLR_SMP_BIT 24*91f16700Schasinglulu stcopr r0, ACTLR 25*91f16700Schasinglulu isb 26*91f16700Schasinglulu dsb sy 27*91f16700Schasinglulu bx lr 28*91f16700Schasingluluendfunc cortex_a5_disable_smp 29*91f16700Schasinglulu 30*91f16700Schasinglulufunc cortex_a5_enable_smp 31*91f16700Schasinglulu ldcopr r0, ACTLR 32*91f16700Schasinglulu orr r0, #CORTEX_A5_ACTLR_SMP_BIT 33*91f16700Schasinglulu stcopr r0, ACTLR 34*91f16700Schasinglulu isb 35*91f16700Schasinglulu bx lr 36*91f16700Schasingluluendfunc cortex_a5_enable_smp 37*91f16700Schasinglulu 38*91f16700Schasinglulufunc cortex_a5_reset_func 39*91f16700Schasinglulu b cortex_a5_enable_smp 40*91f16700Schasingluluendfunc cortex_a5_reset_func 41*91f16700Schasinglulu 42*91f16700Schasinglulufunc cortex_a5_core_pwr_dwn 43*91f16700Schasinglulu push {r12, lr} 44*91f16700Schasinglulu 45*91f16700Schasinglulu assert_cache_enabled 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* Flush L1 cache */ 48*91f16700Schasinglulu mov r0, #DC_OP_CISW 49*91f16700Schasinglulu bl dcsw_op_level1 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* Exit cluster coherency */ 52*91f16700Schasinglulu pop {r12, lr} 53*91f16700Schasinglulu b cortex_a5_disable_smp 54*91f16700Schasingluluendfunc cortex_a5_core_pwr_dwn 55*91f16700Schasinglulu 56*91f16700Schasinglulufunc cortex_a5_cluster_pwr_dwn 57*91f16700Schasinglulu push {r12, lr} 58*91f16700Schasinglulu 59*91f16700Schasinglulu assert_cache_enabled 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* Flush L1 caches */ 62*91f16700Schasinglulu mov r0, #DC_OP_CISW 63*91f16700Schasinglulu bl dcsw_op_level1 64*91f16700Schasinglulu 65*91f16700Schasinglulu bl plat_disable_acp 66*91f16700Schasinglulu 67*91f16700Schasinglulu /* Exit cluster coherency */ 68*91f16700Schasinglulu pop {r12, lr} 69*91f16700Schasinglulu b cortex_a5_disable_smp 70*91f16700Schasingluluendfunc cortex_a5_cluster_pwr_dwn 71*91f16700Schasinglulu 72*91f16700Schasingluluerrata_report_shim cortex_a5 73*91f16700Schasinglulu 74*91f16700Schasingluludeclare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \ 75*91f16700Schasinglulu cortex_a5_reset_func, \ 76*91f16700Schasinglulu cortex_a5_core_pwr_dwn, \ 77*91f16700Schasinglulu cortex_a5_cluster_pwr_dwn 78