1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016-2017, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <aem_generic.h> 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <assert_macros.S> 10*91f16700Schasinglulu#include <cpu_macros.S> 11*91f16700Schasinglulu 12*91f16700Schasinglulufunc aem_generic_core_pwr_dwn 13*91f16700Schasinglulu /* Assert if cache is enabled */ 14*91f16700Schasinglulu#if ENABLE_ASSERTIONS 15*91f16700Schasinglulu ldcopr r0, SCTLR 16*91f16700Schasinglulu tst r0, #SCTLR_C_BIT 17*91f16700Schasinglulu ASM_ASSERT(eq) 18*91f16700Schasinglulu#endif 19*91f16700Schasinglulu /* --------------------------------------------- 20*91f16700Schasinglulu * Flush L1 cache to PoU. 21*91f16700Schasinglulu * --------------------------------------------- 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu mov r0, #DC_OP_CISW 24*91f16700Schasinglulu b dcsw_op_louis 25*91f16700Schasingluluendfunc aem_generic_core_pwr_dwn 26*91f16700Schasinglulu 27*91f16700Schasinglulu 28*91f16700Schasinglulufunc aem_generic_cluster_pwr_dwn 29*91f16700Schasinglulu /* Assert if cache is enabled */ 30*91f16700Schasinglulu#if ENABLE_ASSERTIONS 31*91f16700Schasinglulu ldcopr r0, SCTLR 32*91f16700Schasinglulu tst r0, #SCTLR_C_BIT 33*91f16700Schasinglulu ASM_ASSERT(eq) 34*91f16700Schasinglulu#endif 35*91f16700Schasinglulu /* --------------------------------------------- 36*91f16700Schasinglulu * Flush L1 and L2 caches to PoC. 37*91f16700Schasinglulu * --------------------------------------------- 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu mov r0, #DC_OP_CISW 40*91f16700Schasinglulu b dcsw_op_all 41*91f16700Schasingluluendfunc aem_generic_cluster_pwr_dwn 42*91f16700Schasinglulu 43*91f16700Schasinglulu#if REPORT_ERRATA 44*91f16700Schasinglulu/* 45*91f16700Schasinglulu * Errata printing function for AEM. Must follow AAPCS. 46*91f16700Schasinglulu */ 47*91f16700Schasinglulufunc aem_generic_errata_report 48*91f16700Schasinglulu bx lr 49*91f16700Schasingluluendfunc aem_generic_errata_report 50*91f16700Schasinglulu#endif 51*91f16700Schasinglulu 52*91f16700Schasinglulu/* cpu_ops for Base AEM FVP */ 53*91f16700Schasingluludeclare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ 54*91f16700Schasinglulu aem_generic_core_pwr_dwn, \ 55*91f16700Schasinglulu aem_generic_cluster_pwr_dwn 56