1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PCI_SVC_H 8*91f16700Schasinglulu #define PCI_SVC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* SMCCC PCI platform functions */ 13*91f16700Schasinglulu #define SMC_PCI_VERSION U(0x84000130) 14*91f16700Schasinglulu #define SMC_PCI_FEATURES U(0x84000131) 15*91f16700Schasinglulu #define SMC_PCI_READ U(0x84000132) 16*91f16700Schasinglulu #define SMC_PCI_WRITE U(0x84000133) 17*91f16700Schasinglulu #define SMC_PCI_SEG_INFO U(0x84000134) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define is_pci_fid(_fid) (((_fid) >= SMC_PCI_VERSION) && \ 20*91f16700Schasinglulu ((_fid) <= SMC_PCI_SEG_INFO)) 21*91f16700Schasinglulu 22*91f16700Schasinglulu uint64_t pci_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 23*91f16700Schasinglulu u_register_t x3, u_register_t x4, void *cookie, 24*91f16700Schasinglulu void *handle, u_register_t flags); 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define PCI_ADDR_FUN(dev) ((dev) & U(0x7)) 27*91f16700Schasinglulu #define PCI_ADDR_DEV(dev) (((dev) >> U(3)) & U(0x001F)) 28*91f16700Schasinglulu #define PCI_ADDR_BUS(dev) (((dev) >> U(8)) & U(0x00FF)) 29*91f16700Schasinglulu #define PCI_ADDR_SEG(dev) (((dev) >> U(16)) & U(0xFFFF)) 30*91f16700Schasinglulu #define PCI_OFFSET_MASK U(0xFFF) 31*91f16700Schasinglulu typedef union { 32*91f16700Schasinglulu struct { 33*91f16700Schasinglulu uint16_t minor; 34*91f16700Schasinglulu uint16_t major; 35*91f16700Schasinglulu } __packed; 36*91f16700Schasinglulu uint32_t val; 37*91f16700Schasinglulu } pcie_version; 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* 40*91f16700Schasinglulu * platforms are responsible for providing implementations of these 41*91f16700Schasinglulu * three functions in a manner which conforms to the Arm PCI Configuration 42*91f16700Schasinglulu * Space Access Firmware Interface (DEN0115) and the PCIe specification's 43*91f16700Schasinglulu * sections on PCI configuration access. See the rpi4_pci_svc.c example. 44*91f16700Schasinglulu */ 45*91f16700Schasinglulu uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val); 46*91f16700Schasinglulu uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val); 47*91f16700Schasinglulu uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg); 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* Return codes for Arm PCI Config Space Access Firmware SMC calls */ 50*91f16700Schasinglulu #define SMC_PCI_CALL_SUCCESS U(0) 51*91f16700Schasinglulu #define SMC_PCI_CALL_NOT_SUPPORTED -1 52*91f16700Schasinglulu #define SMC_PCI_CALL_INVAL_PARAM -2 53*91f16700Schasinglulu #define SMC_PCI_CALL_NOT_IMPL -3 54*91f16700Schasinglulu 55*91f16700Schasinglulu #define SMC_PCI_SZ_8BIT U(1) 56*91f16700Schasinglulu #define SMC_PCI_SZ_16BIT U(2) 57*91f16700Schasinglulu #define SMC_PCI_SZ_32BIT U(4) 58*91f16700Schasinglulu 59*91f16700Schasinglulu #endif /* PCI_SVC_H */ 60