1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2016 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PLAT_MARVELL_H 9*91f16700Schasinglulu #define PLAT_MARVELL_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <common/bl_common.h> 14*91f16700Schasinglulu #include <lib/cassert.h> 15*91f16700Schasinglulu #include <lib/el3_runtime/cpu_data.h> 16*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_v2.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* 19*91f16700Schasinglulu * Extern declarations common to Marvell standard platforms 20*91f16700Schasinglulu */ 21*91f16700Schasinglulu extern const mmap_region_t plat_marvell_mmap[]; 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define MARVELL_CASSERT_MMAP \ 24*91f16700Schasinglulu CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \ 25*91f16700Schasinglulu <= MAX_MMAP_REGIONS, \ 26*91f16700Schasinglulu assert_max_mmap_regions) 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* 29*91f16700Schasinglulu * Utility functions common to Marvell standard platforms 30*91f16700Schasinglulu */ 31*91f16700Schasinglulu void marvell_setup_page_tables(uintptr_t total_base, 32*91f16700Schasinglulu size_t total_size, 33*91f16700Schasinglulu uintptr_t code_start, 34*91f16700Schasinglulu uintptr_t code_limit, 35*91f16700Schasinglulu uintptr_t rodata_start, 36*91f16700Schasinglulu uintptr_t rodata_limit 37*91f16700Schasinglulu #if USE_COHERENT_MEM 38*91f16700Schasinglulu , uintptr_t coh_start, 39*91f16700Schasinglulu uintptr_t coh_limit 40*91f16700Schasinglulu #endif 41*91f16700Schasinglulu ); 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* Console utility functions */ 44*91f16700Schasinglulu void marvell_console_boot_init(void); 45*91f16700Schasinglulu void marvell_console_boot_end(void); 46*91f16700Schasinglulu void marvell_console_runtime_init(void); 47*91f16700Schasinglulu void marvell_console_runtime_end(void); 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* IO storage utility functions */ 50*91f16700Schasinglulu void marvell_io_setup(void); 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* Systimer utility function */ 53*91f16700Schasinglulu void marvell_configure_sys_timer(void); 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* Topology utility function */ 56*91f16700Schasinglulu int marvell_check_mpidr(u_register_t mpidr); 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* BL1 utility functions */ 59*91f16700Schasinglulu void marvell_bl1_early_platform_setup(void); 60*91f16700Schasinglulu void marvell_bl1_platform_setup(void); 61*91f16700Schasinglulu void marvell_bl1_plat_arch_setup(void); 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* BL2 utility functions */ 64*91f16700Schasinglulu void marvell_bl2_early_platform_setup(meminfo_t *mem_layout); 65*91f16700Schasinglulu void marvell_bl2_platform_setup(void); 66*91f16700Schasinglulu void marvell_bl2_plat_arch_setup(void); 67*91f16700Schasinglulu uint32_t marvell_get_spsr_for_bl32_entry(void); 68*91f16700Schasinglulu uint32_t marvell_get_spsr_for_bl33_entry(void); 69*91f16700Schasinglulu 70*91f16700Schasinglulu /* BL31 utility functions */ 71*91f16700Schasinglulu void marvell_bl31_early_platform_setup(void *from_bl2, 72*91f16700Schasinglulu uintptr_t soc_fw_config, 73*91f16700Schasinglulu uintptr_t hw_config, 74*91f16700Schasinglulu void *plat_params_from_bl2); 75*91f16700Schasinglulu void marvell_bl31_platform_setup(void); 76*91f16700Schasinglulu void marvell_bl31_plat_runtime_setup(void); 77*91f16700Schasinglulu void marvell_bl31_plat_arch_setup(void); 78*91f16700Schasinglulu 79*91f16700Schasinglulu /* FIP TOC validity check */ 80*91f16700Schasinglulu int marvell_io_is_toc_valid(void); 81*91f16700Schasinglulu 82*91f16700Schasinglulu /* 83*91f16700Schasinglulu * PSCI functionality 84*91f16700Schasinglulu */ 85*91f16700Schasinglulu void marvell_psci_arch_init(int idx); 86*91f16700Schasinglulu void plat_marvell_system_reset(void); 87*91f16700Schasinglulu 88*91f16700Schasinglulu /* 89*91f16700Schasinglulu * Optional functions required in Marvell standard platforms 90*91f16700Schasinglulu */ 91*91f16700Schasinglulu void plat_marvell_io_setup(void); 92*91f16700Schasinglulu int plat_marvell_get_alt_image_source( 93*91f16700Schasinglulu unsigned int image_id, 94*91f16700Schasinglulu uintptr_t *dev_handle, 95*91f16700Schasinglulu uintptr_t *image_spec); 96*91f16700Schasinglulu unsigned int plat_marvell_calc_core_pos(u_register_t mpidr); 97*91f16700Schasinglulu 98*91f16700Schasinglulu void plat_marvell_interconnect_init(void); 99*91f16700Schasinglulu void plat_marvell_interconnect_enter_coherency(void); 100*91f16700Schasinglulu 101*91f16700Schasinglulu const mmap_region_t *plat_marvell_get_mmap(void); 102*91f16700Schasinglulu 103*91f16700Schasinglulu uint32_t get_ref_clk(void); 104*91f16700Schasinglulu 105*91f16700Schasinglulu #endif /* PLAT_MARVELL_H */ 106