1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_DRTM_H 8*91f16700Schasinglulu #define PLAT_DRTM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_compat.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu typedef struct { 14*91f16700Schasinglulu uint8_t max_num_mem_prot_regions; 15*91f16700Schasinglulu uint8_t dma_protection_support; 16*91f16700Schasinglulu } plat_drtm_dma_prot_features_t; 17*91f16700Schasinglulu 18*91f16700Schasinglulu typedef struct { 19*91f16700Schasinglulu bool tpm_based_hash_support; 20*91f16700Schasinglulu uint32_t firmware_hash_algorithm; 21*91f16700Schasinglulu } plat_drtm_tpm_features_t; 22*91f16700Schasinglulu 23*91f16700Schasinglulu typedef struct { 24*91f16700Schasinglulu uint64_t region_address; 25*91f16700Schasinglulu uint64_t region_size_type; 26*91f16700Schasinglulu } __attribute__((packed)) drtm_mem_region_t; 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* 29*91f16700Schasinglulu * Memory region descriptor table structure as per DRTM beta0 section 3.13 30*91f16700Schasinglulu * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu typedef struct { 33*91f16700Schasinglulu uint16_t revision; 34*91f16700Schasinglulu uint16_t reserved; 35*91f16700Schasinglulu uint32_t num_regions; 36*91f16700Schasinglulu drtm_mem_region_t region[]; 37*91f16700Schasinglulu } __attribute__((packed)) drtm_memory_region_descriptor_table_t; 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* platform specific address map functions */ 40*91f16700Schasinglulu const mmap_region_t *plat_get_addr_mmap(void); 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* platform-specific DMA protection functions */ 43*91f16700Schasinglulu bool plat_has_non_host_platforms(void); 44*91f16700Schasinglulu bool plat_has_unmanaged_dma_peripherals(void); 45*91f16700Schasinglulu unsigned int plat_get_total_smmus(void); 46*91f16700Schasinglulu void plat_enumerate_smmus(const uintptr_t **smmus_out, 47*91f16700Schasinglulu size_t *smmu_count_out); 48*91f16700Schasinglulu const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void); 49*91f16700Schasinglulu uint64_t plat_drtm_dma_prot_get_max_table_bytes(void); 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* platform-specific TPM functions */ 52*91f16700Schasinglulu const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void); 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* 55*91f16700Schasinglulu * TODO: Implement these functions as per the platform use case, 56*91f16700Schasinglulu * as of now none of the platform uses these functions 57*91f16700Schasinglulu */ 58*91f16700Schasinglulu uint64_t plat_drtm_get_min_size_normal_world_dce(void); 59*91f16700Schasinglulu uint64_t plat_drtm_get_tcb_hash_table_size(void); 60*91f16700Schasinglulu uint64_t plat_drtm_get_imp_def_dlme_region_size(void); 61*91f16700Schasinglulu uint64_t plat_drtm_get_tcb_hash_features(void); 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* DRTM error handling functions */ 64*91f16700Schasinglulu int plat_set_drtm_error(uint64_t error_code); 65*91f16700Schasinglulu int plat_get_drtm_error(uint64_t *error_code); 66*91f16700Schasinglulu 67*91f16700Schasinglulu /* 68*91f16700Schasinglulu * Platform-specific function to ensure passed region lies within 69*91f16700Schasinglulu * Non-Secure region of DRAM 70*91f16700Schasinglulu */ 71*91f16700Schasinglulu int plat_drtm_validate_ns_region(uintptr_t region_start, 72*91f16700Schasinglulu size_t region_size); 73*91f16700Schasinglulu 74*91f16700Schasinglulu #endif /* PLAT_DRTM_H */ 75