1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #ifndef COMMON_DEF_H 7*91f16700Schasinglulu #define COMMON_DEF_H 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/bl_common.h> 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_defs.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define SZ_32 U(0x00000020) 16*91f16700Schasinglulu #define SZ_64 U(0x00000040) 17*91f16700Schasinglulu #define SZ_128 U(0x00000080) 18*91f16700Schasinglulu #define SZ_256 U(0x00000100) 19*91f16700Schasinglulu #define SZ_512 U(0x00000200) 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define SZ_1K U(0x00000400) 22*91f16700Schasinglulu #define SZ_2K U(0x00000800) 23*91f16700Schasinglulu #define SZ_4K U(0x00001000) 24*91f16700Schasinglulu #define SZ_8K U(0x00002000) 25*91f16700Schasinglulu #define SZ_16K U(0x00004000) 26*91f16700Schasinglulu #define SZ_32K U(0x00008000) 27*91f16700Schasinglulu #define SZ_64K U(0x00010000) 28*91f16700Schasinglulu #define SZ_128K U(0x00020000) 29*91f16700Schasinglulu #define SZ_256K U(0x00040000) 30*91f16700Schasinglulu #define SZ_512K U(0x00080000) 31*91f16700Schasinglulu 32*91f16700Schasinglulu #define SZ_1M U(0x00100000) 33*91f16700Schasinglulu #define SZ_2M U(0x00200000) 34*91f16700Schasinglulu #define SZ_4M U(0x00400000) 35*91f16700Schasinglulu #define SZ_8M U(0x00800000) 36*91f16700Schasinglulu #define SZ_16M U(0x01000000) 37*91f16700Schasinglulu #define SZ_32M U(0x02000000) 38*91f16700Schasinglulu #define SZ_64M U(0x04000000) 39*91f16700Schasinglulu #define SZ_128M U(0x08000000) 40*91f16700Schasinglulu #define SZ_256M U(0x10000000) 41*91f16700Schasinglulu #define SZ_512M U(0x20000000) 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define SZ_1G U(0x40000000) 44*91f16700Schasinglulu #define SZ_2G U(0x80000000) 45*91f16700Schasinglulu 46*91f16700Schasinglulu /****************************************************************************** 47*91f16700Schasinglulu * Required platform porting definitions that are expected to be common to 48*91f16700Schasinglulu * all platforms 49*91f16700Schasinglulu *****************************************************************************/ 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* 52*91f16700Schasinglulu * Platform binary types for linking 53*91f16700Schasinglulu */ 54*91f16700Schasinglulu #ifdef __aarch64__ 55*91f16700Schasinglulu #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 56*91f16700Schasinglulu #define PLATFORM_LINKER_ARCH aarch64 57*91f16700Schasinglulu #else 58*91f16700Schasinglulu #define PLATFORM_LINKER_FORMAT "elf32-littlearm" 59*91f16700Schasinglulu #define PLATFORM_LINKER_ARCH arm 60*91f16700Schasinglulu #endif /* __aarch64__ */ 61*91f16700Schasinglulu 62*91f16700Schasinglulu /* 63*91f16700Schasinglulu * Generic platform constants 64*91f16700Schasinglulu */ 65*91f16700Schasinglulu #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define BL2_IMAGE_DESC { \ 68*91f16700Schasinglulu .image_id = BL2_IMAGE_ID, \ 69*91f16700Schasinglulu SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ 70*91f16700Schasinglulu VERSION_2, image_info_t, 0), \ 71*91f16700Schasinglulu .image_info.image_base = BL2_BASE, \ 72*91f16700Schasinglulu .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\ 73*91f16700Schasinglulu SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ 74*91f16700Schasinglulu VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ 75*91f16700Schasinglulu .ep_info.pc = BL2_BASE, \ 76*91f16700Schasinglulu } 77*91f16700Schasinglulu 78*91f16700Schasinglulu /* 79*91f16700Schasinglulu * The following constants identify the extents of the code & read-only data 80*91f16700Schasinglulu * regions. These addresses are used by the MMU setup code and therefore they 81*91f16700Schasinglulu * must be page-aligned. 82*91f16700Schasinglulu * 83*91f16700Schasinglulu * When the code and read-only data are mapped as a single atomic section 84*91f16700Schasinglulu * (i.e. when SEPARATE_CODE_AND_RODATA=0) then we treat the whole section as 85*91f16700Schasinglulu * code by specifying the read-only data section as empty. 86*91f16700Schasinglulu * 87*91f16700Schasinglulu * BL1 is different than the other images in the sense that its read-write data 88*91f16700Schasinglulu * originally lives in Trusted ROM and needs to be relocated in Trusted SRAM at 89*91f16700Schasinglulu * run-time. Therefore, the read-write data in ROM can be mapped with the same 90*91f16700Schasinglulu * memory attributes as the read-only data region. For this reason, BL1 uses 91*91f16700Schasinglulu * different macros. 92*91f16700Schasinglulu * 93*91f16700Schasinglulu * Note that BL1_ROM_END is not necessarily aligned on a page boundary as it 94*91f16700Schasinglulu * just points to the end of BL1's actual content in Trusted ROM. Therefore it 95*91f16700Schasinglulu * needs to be rounded up to the next page size in order to map the whole last 96*91f16700Schasinglulu * page of it with the right memory attributes. 97*91f16700Schasinglulu */ 98*91f16700Schasinglulu #if SEPARATE_CODE_AND_RODATA 99*91f16700Schasinglulu 100*91f16700Schasinglulu #define BL1_CODE_END BL_CODE_END 101*91f16700Schasinglulu #define BL1_RO_DATA_BASE BL_RO_DATA_BASE 102*91f16700Schasinglulu #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) 103*91f16700Schasinglulu #if BL2_IN_XIP_MEM 104*91f16700Schasinglulu #define BL2_CODE_END BL_CODE_END 105*91f16700Schasinglulu #define BL2_RO_DATA_BASE BL_RO_DATA_BASE 106*91f16700Schasinglulu #define BL2_RO_DATA_END round_up(BL2_ROM_END, PAGE_SIZE) 107*91f16700Schasinglulu #endif /* BL2_IN_XIP_MEM */ 108*91f16700Schasinglulu #else 109*91f16700Schasinglulu #define BL_RO_DATA_BASE UL(0) 110*91f16700Schasinglulu #define BL_RO_DATA_END UL(0) 111*91f16700Schasinglulu #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) 112*91f16700Schasinglulu #if BL2_IN_XIP_MEM 113*91f16700Schasinglulu #define BL2_RO_DATA_BASE UL(0) 114*91f16700Schasinglulu #define BL2_RO_DATA_END UL(0) 115*91f16700Schasinglulu #define BL2_CODE_END round_up(BL2_ROM_END, PAGE_SIZE) 116*91f16700Schasinglulu #endif /* BL2_IN_XIP_MEM */ 117*91f16700Schasinglulu #endif /* SEPARATE_CODE_AND_RODATA */ 118*91f16700Schasinglulu 119*91f16700Schasinglulu #if MEASURED_BOOT 120*91f16700Schasinglulu /* 121*91f16700Schasinglulu * Start critical data Ids from 2^32/2 reserving Ids from 0 to (2^32/2 - 1) 122*91f16700Schasinglulu * for Images, It is a critical data Id base for all platforms. 123*91f16700Schasinglulu */ 124*91f16700Schasinglulu #define CRITICAL_DATA_ID_BASE U(0x80000000) 125*91f16700Schasinglulu #endif /* MEASURED_BOOT */ 126*91f16700Schasinglulu 127*91f16700Schasinglulu #endif /* COMMON_DEF_H */ 128