1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SOC_CSS_DEF_H 8*91f16700Schasinglulu #define SOC_CSS_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu #include <plat/common/common_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* 14*91f16700Schasinglulu * Definitions common to all ARM CSS SoCs 15*91f16700Schasinglulu */ 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* Following covers ARM CSS SoC Peripherals and PCIe expansion area */ 18*91f16700Schasinglulu #define SOC_CSS_DEVICE_BASE 0x40000000 19*91f16700Schasinglulu #define SOC_CSS_DEVICE_SIZE 0x40000000 20*91f16700Schasinglulu #define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* PL011 UART related constants */ 23*91f16700Schasinglulu #define SOC_CSS_UART0_BASE 0x7ff80000 24*91f16700Schasinglulu #define SOC_CSS_UART1_BASE 0x7ff70000 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define SOC_CSS_UART0_CLK_IN_HZ 7372800 27*91f16700Schasinglulu #define SOC_CSS_UART1_CLK_IN_HZ 7372800 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* SoC NIC-400 Global Programmers View (GPV) */ 30*91f16700Schasinglulu #define SOC_CSS_NIC400_BASE 0x7fd00000 31*91f16700Schasinglulu 32*91f16700Schasinglulu #define SOC_CSS_NIC400_USB_EHCI 0 33*91f16700Schasinglulu #define SOC_CSS_NIC400_TLX_MASTER 1 34*91f16700Schasinglulu #define SOC_CSS_NIC400_USB_OHCI 2 35*91f16700Schasinglulu #define SOC_CSS_NIC400_PL354_SMC 3 36*91f16700Schasinglulu /* 37*91f16700Schasinglulu * The apb4_bridge controls access to: 38*91f16700Schasinglulu * - the PCIe configuration registers 39*91f16700Schasinglulu * - the MMU units for USB, HDLCD and DMA 40*91f16700Schasinglulu */ 41*91f16700Schasinglulu #define SOC_CSS_NIC400_APB4_BRIDGE 4 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* Non-volatile counters */ 44*91f16700Schasinglulu #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 45*91f16700Schasinglulu #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 46*91f16700Schasinglulu #define TFW_NVCTR_SIZE 4 47*91f16700Schasinglulu #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 48*91f16700Schasinglulu #define NTFW_CTR_SIZE 4 49*91f16700Schasinglulu 50*91f16700Schasinglulu /* Keys */ 51*91f16700Schasinglulu #define SOC_KEYS_BASE 0x7fe80000 52*91f16700Schasinglulu #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 53*91f16700Schasinglulu #define TZ_PUB_KEY_HASH_SIZE 32 54*91f16700Schasinglulu #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 55*91f16700Schasinglulu #define HU_KEY_SIZE 16 56*91f16700Schasinglulu #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 57*91f16700Schasinglulu #define END_KEY_SIZE 32 58*91f16700Schasinglulu 59*91f16700Schasinglulu #define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \ 60*91f16700Schasinglulu SOC_CSS_DEVICE_BASE, \ 61*91f16700Schasinglulu SOC_CSS_DEVICE_SIZE, \ 62*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 63*91f16700Schasinglulu 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* 66*91f16700Schasinglulu * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. 67*91f16700Schasinglulu */ 68*91f16700Schasinglulu #define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5 69*91f16700Schasinglulu #define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) 70*91f16700Schasinglulu 71*91f16700Schasinglulu /* 72*91f16700Schasinglulu * Required platform porting definitions common to all ARM CSS SoCs 73*91f16700Schasinglulu */ 74*91f16700Schasinglulu #if JUNO_AARCH32_EL3_RUNTIME 75*91f16700Schasinglulu /* 76*91f16700Schasinglulu * Following change is required to initialize TZC 77*91f16700Schasinglulu * for enabling access to the HI_VECTOR (0xFFFF0000) 78*91f16700Schasinglulu * location needed for JUNO AARCH32 support. 79*91f16700Schasinglulu */ 80*91f16700Schasinglulu #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000) 81*91f16700Schasinglulu #else 82*91f16700Schasinglulu /* 2MB used for SCP DDR retraining */ 83*91f16700Schasinglulu #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) 84*91f16700Schasinglulu #endif 85*91f16700Schasinglulu 86*91f16700Schasinglulu #endif /* SOC_CSS_DEF_H */ 87