1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#ifndef ARM_TZC_DRAM_LD_S 7*91f16700Schasinglulu#define ARM_TZC_DRAM_LD_S 8*91f16700Schasinglulu 9*91f16700Schasinglulu#include <lib/xlat_tables/xlat_tables_defs.h> 10*91f16700Schasinglulu 11*91f16700SchasingluluMEMORY { 12*91f16700Schasinglulu EL3_SEC_DRAM (rw): ORIGIN = ARM_EL3_TZC_DRAM1_BASE, LENGTH = ARM_EL3_TZC_DRAM1_SIZE 13*91f16700Schasinglulu} 14*91f16700Schasinglulu 15*91f16700SchasingluluSECTIONS 16*91f16700Schasinglulu{ 17*91f16700Schasinglulu . = ARM_EL3_TZC_DRAM1_BASE; 18*91f16700Schasinglulu ASSERT(. == ALIGN(PAGE_SIZE), 19*91f16700Schasinglulu "ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.") 20*91f16700Schasinglulu .el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) { 21*91f16700Schasinglulu __EL3_SEC_DRAM_START__ = .; 22*91f16700Schasinglulu *(.arm_el3_tzc_dram) 23*91f16700Schasinglulu __EL3_SEC_DRAM_UNALIGNED_END__ = .; 24*91f16700Schasinglulu 25*91f16700Schasinglulu . = ALIGN(PAGE_SIZE); 26*91f16700Schasinglulu __EL3_SEC_DRAM_END__ = .; 27*91f16700Schasinglulu } >EL3_SEC_DRAM 28*91f16700Schasinglulu} 29*91f16700Schasinglulu 30*91f16700Schasinglulu#endif /* ARM_TZC_DRAM_LD_S */ 31