1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#ifndef CCI_MACROS_S 7*91f16700Schasinglulu#define CCI_MACROS_S 8*91f16700Schasinglulu 9*91f16700Schasinglulu#include <drivers/arm/cci.h> 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu.section .rodata.cci_reg_name, "aS" 13*91f16700Schasinglulucci_iface_regs: 14*91f16700Schasinglulu .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* ------------------------------------------------ 17*91f16700Schasinglulu * The below required platform porting macro prints 18*91f16700Schasinglulu * out relevant interconnect registers whenever an 19*91f16700Schasinglulu * unhandled exception is taken in BL31. 20*91f16700Schasinglulu * Clobbers: x0 - x9, sp 21*91f16700Schasinglulu * ------------------------------------------------ 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu .macro print_cci_regs 24*91f16700Schasinglulu adr x6, cci_iface_regs 25*91f16700Schasinglulu /* Store in x7 the base address of the first interface */ 26*91f16700Schasinglulu mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ 27*91f16700Schasinglulu PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX)) 28*91f16700Schasinglulu ldr w8, [x7, #SNOOP_CTRL_REG] 29*91f16700Schasinglulu /* Store in x7 the base address of the second interface */ 30*91f16700Schasinglulu mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ 31*91f16700Schasinglulu PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX)) 32*91f16700Schasinglulu ldr w9, [x7, #SNOOP_CTRL_REG] 33*91f16700Schasinglulu /* Store to the crash buf and print to console */ 34*91f16700Schasinglulu bl str_in_crash_buf_print 35*91f16700Schasinglulu .endm 36*91f16700Schasinglulu 37*91f16700Schasinglulu#endif /* CCI_MACROS_S */ 38