1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#ifndef ARM_MACROS_S 7*91f16700Schasinglulu#define ARM_MACROS_S 8*91f16700Schasinglulu 9*91f16700Schasinglulu#include <drivers/arm/gic_common.h> 10*91f16700Schasinglulu#include <drivers/arm/gicv2.h> 11*91f16700Schasinglulu#include <drivers/arm/gicv3.h> 12*91f16700Schasinglulu#include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu.section .rodata.gic_reg_name, "aS" 15*91f16700Schasinglulu/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 16*91f16700Schasinglulugicc_regs: 17*91f16700Schasinglulu .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* Applicable only to GICv3 with SRE enabled */ 20*91f16700Schasingluluicc_regs: 21*91f16700Schasinglulu .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 22*91f16700Schasinglulu 23*91f16700Schasinglulu/* Registers common to both GICv2 and GICv3 */ 24*91f16700Schasinglulugicd_pend_reg: 25*91f16700Schasinglulu .asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n" 26*91f16700Schasinglulunewline: 27*91f16700Schasinglulu .asciz "\n" 28*91f16700Schasingluluspacer: 29*91f16700Schasinglulu .asciz ":\t\t 0x" 30*91f16700Schasingluluprefix: 31*91f16700Schasinglulu .asciz "0x" 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* --------------------------------------------- 34*91f16700Schasinglulu * The below utility macro prints out relevant GIC 35*91f16700Schasinglulu * registers whenever an unhandled exception is 36*91f16700Schasinglulu * taken in BL31 on ARM standard platforms. 37*91f16700Schasinglulu * Expects: GICD base in x16, GICC base in x17 38*91f16700Schasinglulu * Clobbers: x0 - x10, sp 39*91f16700Schasinglulu * --------------------------------------------- 40*91f16700Schasinglulu */ 41*91f16700Schasinglulu .macro arm_print_gic_regs 42*91f16700Schasinglulu /* Check for GICv3/v4 system register access. 43*91f16700Schasinglulu * ID_AA64PFR0_GIC indicates presence of the CPU 44*91f16700Schasinglulu * system registers by either 0b0011 or 0xb0001. 45*91f16700Schasinglulu * A value of 0b000 means CPU system registers aren't 46*91f16700Schasinglulu * available and the code needs to use the memory 47*91f16700Schasinglulu * mapped registers like in GICv2. 48*91f16700Schasinglulu */ 49*91f16700Schasinglulu mrs x7, id_aa64pfr0_el1 50*91f16700Schasinglulu ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 51*91f16700Schasinglulu cmp x7, #0 52*91f16700Schasinglulu b.eq print_gicv2 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* Check for SRE enable */ 55*91f16700Schasinglulu mrs x8, ICC_SRE_EL3 56*91f16700Schasinglulu tst x8, #ICC_SRE_SRE_BIT 57*91f16700Schasinglulu b.eq print_gicv2 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* Load the icc reg list to x6 */ 60*91f16700Schasinglulu adr x6, icc_regs 61*91f16700Schasinglulu /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 62*91f16700Schasinglulu mrs x8, ICC_HPPIR0_EL1 63*91f16700Schasinglulu mrs x9, ICC_HPPIR1_EL1 64*91f16700Schasinglulu mrs x10, ICC_CTLR_EL3 65*91f16700Schasinglulu /* Store to the crash buf and print to console */ 66*91f16700Schasinglulu bl str_in_crash_buf_print 67*91f16700Schasinglulu b print_gic_common 68*91f16700Schasinglulu 69*91f16700Schasingluluprint_gicv2: 70*91f16700Schasinglulu /* Load the gicc reg list to x6 */ 71*91f16700Schasinglulu adr x6, gicc_regs 72*91f16700Schasinglulu /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 73*91f16700Schasinglulu ldr w8, [x17, #GICC_HPPIR] 74*91f16700Schasinglulu ldr w9, [x17, #GICC_AHPPIR] 75*91f16700Schasinglulu ldr w10, [x17, #GICC_CTLR] 76*91f16700Schasinglulu /* Store to the crash buf and print to console */ 77*91f16700Schasinglulu bl str_in_crash_buf_print 78*91f16700Schasinglulu 79*91f16700Schasingluluprint_gic_common: 80*91f16700Schasinglulu /* Print the GICD_ISPENDR regs */ 81*91f16700Schasinglulu add x7, x16, #GICD_ISPENDR 82*91f16700Schasinglulu adr x4, gicd_pend_reg 83*91f16700Schasinglulu bl asm_print_str 84*91f16700Schasinglulugicd_ispendr_loop: 85*91f16700Schasinglulu sub x4, x7, x16 86*91f16700Schasinglulu cmp x4, #0x280 87*91f16700Schasinglulu b.eq exit_print_gic_regs 88*91f16700Schasinglulu 89*91f16700Schasinglulu /* Print "0x" */ 90*91f16700Schasinglulu adr x4, prefix 91*91f16700Schasinglulu bl asm_print_str 92*91f16700Schasinglulu 93*91f16700Schasinglulu /* Print offset */ 94*91f16700Schasinglulu sub x4, x7, x16 95*91f16700Schasinglulu mov x5, #12 96*91f16700Schasinglulu bl asm_print_hex_bits 97*91f16700Schasinglulu 98*91f16700Schasinglulu adr x4, spacer 99*91f16700Schasinglulu bl asm_print_str 100*91f16700Schasinglulu 101*91f16700Schasinglulu ldr x4, [x7], #8 102*91f16700Schasinglulu bl asm_print_hex 103*91f16700Schasinglulu 104*91f16700Schasinglulu adr x4, newline 105*91f16700Schasinglulu bl asm_print_str 106*91f16700Schasinglulu b gicd_ispendr_loop 107*91f16700Schasingluluexit_print_gic_regs: 108*91f16700Schasinglulu .endm 109*91f16700Schasinglulu 110*91f16700Schasinglulu#endif /* ARM_MACROS_S */ 111