1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef BOARD_CSS_DEF_H 8*91f16700Schasinglulu #define BOARD_CSS_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu #include <plat/arm/board/common/v2m_def.h> 12*91f16700Schasinglulu #include <plat/arm/soc/common/soc_css_def.h> 13*91f16700Schasinglulu #include <plat/common/common_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* 16*91f16700Schasinglulu * Definitions common to all ARM CSS-based development platforms 17*91f16700Schasinglulu */ 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* Platform ID address */ 20*91f16700Schasinglulu #define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* Platform ID related accessors */ 23*91f16700Schasinglulu #define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f 24*91f16700Schasinglulu #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 25*91f16700Schasinglulu #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 26*91f16700Schasinglulu #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 27*91f16700Schasinglulu #define BOARD_CSS_PLAT_TYPE_RTL 0x00 28*91f16700Schasinglulu #define BOARD_CSS_PLAT_TYPE_FPGA 0x01 29*91f16700Schasinglulu #define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 30*91f16700Schasinglulu #define BOARD_CSS_PLAT_TYPE_FVP 0x03 31*91f16700Schasinglulu 32*91f16700Schasinglulu #ifndef __ASSEMBLER__ 33*91f16700Schasinglulu 34*91f16700Schasinglulu #include <lib/mmio.h> 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 37*91f16700Schasinglulu ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 38*91f16700Schasinglulu >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 39*91f16700Schasinglulu 40*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 41*91f16700Schasinglulu 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define MAX_IO_DEVICES 3 44*91f16700Schasinglulu #define MAX_IO_HANDLES 4 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 47*91f16700Schasinglulu #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 48*91f16700Schasinglulu #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 49*91f16700Schasinglulu 50*91f16700Schasinglulu #if ARM_GPT_SUPPORT 51*91f16700Schasinglulu /* 52*91f16700Schasinglulu * Offset of the FIP in the GPT image. BL1 component uses this option 53*91f16700Schasinglulu * as it does not load the partition table to get the FIP base 54*91f16700Schasinglulu * address. At sector 34 by default (i.e. after reserved sectors 0-33) 55*91f16700Schasinglulu * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 58*91f16700Schasinglulu #endif /* ARM_GPT_SUPPORT */ 59*91f16700Schasinglulu 60*91f16700Schasinglulu #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 61*91f16700Schasinglulu #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* UART related constants */ 64*91f16700Schasinglulu #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE 65*91f16700Schasinglulu #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE 68*91f16700Schasinglulu #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 69*91f16700Schasinglulu 70*91f16700Schasinglulu #define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE 71*91f16700Schasinglulu #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 72*91f16700Schasinglulu 73*91f16700Schasinglulu #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 74*91f16700Schasinglulu #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 75*91f16700Schasinglulu 76*91f16700Schasinglulu #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE 77*91f16700Schasinglulu #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 78*91f16700Schasinglulu 79*91f16700Schasinglulu #endif /* BOARD_CSS_DEF_H */ 80