1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef XLAT_TABLES_AARCH32_H 8*91f16700Schasinglulu #define XLAT_TABLES_AARCH32_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_defs.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #if !defined(PAGE_SIZE) 15*91f16700Schasinglulu #error "PAGE_SIZE is not defined." 16*91f16700Schasinglulu #endif 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* 19*91f16700Schasinglulu * In AArch32 state, the MMU only supports 4KB page granularity, which means 20*91f16700Schasinglulu * that the first translation table level is either 1 or 2. Both of them are 21*91f16700Schasinglulu * allowed to have block and table descriptors. See section G4.5.6 of the 22*91f16700Schasinglulu * ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information. 23*91f16700Schasinglulu * 24*91f16700Schasinglulu * The define below specifies the first table level that allows block 25*91f16700Schasinglulu * descriptors. 26*91f16700Schasinglulu */ 27*91f16700Schasinglulu #if PAGE_SIZE != PAGE_SIZE_4KB 28*91f16700Schasinglulu #error "Invalid granule size. AArch32 supports 4KB pages only." 29*91f16700Schasinglulu #endif 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define MIN_LVL_BLOCK_DESC U(1) 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define XLAT_TABLE_LEVEL_MIN U(1) 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* 36*91f16700Schasinglulu * Define the architectural limits of the virtual address space in AArch32 37*91f16700Schasinglulu * state. 38*91f16700Schasinglulu * 39*91f16700Schasinglulu * TTBCR.TxSZ is calculated as 32 minus the width of said address space. The 40*91f16700Schasinglulu * value of TTBCR.TxSZ must be in the range 0 to 7 [1], which means that the 41*91f16700Schasinglulu * virtual address space width must be in the range 32 to 25 bits. 42*91f16700Schasinglulu * 43*91f16700Schasinglulu * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 44*91f16700Schasinglulu * information, Section G4.6.5 45*91f16700Schasinglulu */ 46*91f16700Schasinglulu #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(32) - TTBCR_TxSZ_MAX)) 47*91f16700Schasinglulu #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(32) - TTBCR_TxSZ_MIN)) 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* 50*91f16700Schasinglulu * Here we calculate the initial lookup level from the value of the given 51*91f16700Schasinglulu * virtual address space size. For a 4 KB page size, 52*91f16700Schasinglulu * - level 1 supports virtual address spaces of widths 32 to 31 bits; 53*91f16700Schasinglulu * - level 2 from 30 to 25. 54*91f16700Schasinglulu * 55*91f16700Schasinglulu * Wider or narrower address spaces are not supported. As a result, level 3 56*91f16700Schasinglulu * cannot be used as the initial lookup level with 4 KB granularity. 57*91f16700Schasinglulu * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 58*91f16700Schasinglulu * information, Section G4.6.5 59*91f16700Schasinglulu * 60*91f16700Schasinglulu * For example, for a 31-bit address space (i.e. virt_addr_space_size == 61*91f16700Schasinglulu * 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table 62*91f16700Schasinglulu * G4-5 in the ARM ARM, the initial lookup level for an address space like that 63*91f16700Schasinglulu * is 1. 64*91f16700Schasinglulu * 65*91f16700Schasinglulu * Note that this macro assumes that the given virtual address space size is 66*91f16700Schasinglulu * valid. 67*91f16700Schasinglulu */ 68*91f16700Schasinglulu #define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz) \ 69*91f16700Schasinglulu (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? \ 70*91f16700Schasinglulu U(1) : U(2)) 71*91f16700Schasinglulu 72*91f16700Schasinglulu #endif /* XLAT_TABLES_AARCH32_H */ 73