1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MPMM_H 8*91f16700Schasinglulu #define MPMM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdbool.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* 15*91f16700Schasinglulu * Enable the Maximum Power Mitigation Mechanism. 16*91f16700Schasinglulu * 17*91f16700Schasinglulu * This function will enable MPMM for the current core. The AMU counters 18*91f16700Schasinglulu * representing the MPMM gears must have been configured and enabled prior to 19*91f16700Schasinglulu * calling this function. 20*91f16700Schasinglulu */ 21*91f16700Schasinglulu void mpmm_enable(void); 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* 24*91f16700Schasinglulu * MPMM core data. 25*91f16700Schasinglulu * 26*91f16700Schasinglulu * This structure represents per-core data retrieved from the hardware 27*91f16700Schasinglulu * configuration device tree. 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu struct mpmm_core { 30*91f16700Schasinglulu /* 31*91f16700Schasinglulu * Whether MPMM is supported. 32*91f16700Schasinglulu * 33*91f16700Schasinglulu * Cores with support for MPMM offer one or more auxiliary AMU counters 34*91f16700Schasinglulu * representing MPMM gears. 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu bool supported; 37*91f16700Schasinglulu }; 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* 40*91f16700Schasinglulu * MPMM topology. 41*91f16700Schasinglulu * 42*91f16700Schasinglulu * This topology structure describes the system-wide representation of the 43*91f16700Schasinglulu * information retrieved from the hardware configuration device tree. 44*91f16700Schasinglulu */ 45*91f16700Schasinglulu struct mpmm_topology { 46*91f16700Schasinglulu struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ 47*91f16700Schasinglulu }; 48*91f16700Schasinglulu 49*91f16700Schasinglulu #if !ENABLE_MPMM_FCONF 50*91f16700Schasinglulu /* 51*91f16700Schasinglulu * Retrieve the platform's MPMM topology. A `NULL` return value is treated as a 52*91f16700Schasinglulu * non-fatal error, in which case MPMM will not be enabled for any core. 53*91f16700Schasinglulu */ 54*91f16700Schasinglulu const struct mpmm_topology *plat_mpmm_topology(void); 55*91f16700Schasinglulu #endif /* ENABLE_MPMM_FCONF */ 56*91f16700Schasinglulu 57*91f16700Schasinglulu #endif /* MPMM_H */ 58