1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef TRAVIS_H 8*91f16700Schasinglulu #define TRAVIS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define TRAVIS_MIDR U(0x410FD8C0) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************************* 13*91f16700Schasinglulu * CPU Extended Control register specific definitions 14*91f16700Schasinglulu ******************************************************************************/ 15*91f16700Schasinglulu #define TRAVIS_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * CPU Power Control register specific definitions 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu #define TRAVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21*91f16700Schasinglulu #define TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22*91f16700Schasinglulu 23*91f16700Schasinglulu /******************************************************************************* 24*91f16700Schasinglulu * SME Control registers 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu #define TRAVIS_SVCRSM S0_3_C4_C2_3 27*91f16700Schasinglulu #define TRAVIS_SVCRZA S0_3_C4_C4_3 28*91f16700Schasinglulu 29*91f16700Schasinglulu #endif /* TRAVIS_H */ 30