1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef RAINIER_H 8*91f16700Schasinglulu #define RAINIER_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* RAINIER MIDR for revision 0 */ 13*91f16700Schasinglulu #define RAINIER_MIDR U(0x3f0f4120) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Exception Syndrome register EC code for IC Trap */ 16*91f16700Schasinglulu #define RAINIER_EC_IC_TRAP U(0x1f) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * CPU Power Control register specific definitions. 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu #define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */ 24*91f16700Schasinglulu #define RAINIER_CORE_PWRDN_EN_MASK U(0x1) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define RAINIER_ACTLR_AMEN_BIT (U(1) << 4) 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define RAINIER_AMU_NR_COUNTERS U(5) 29*91f16700Schasinglulu #define RAINIER_AMU_GROUP0_MASK U(0x1f) 30*91f16700Schasinglulu 31*91f16700Schasinglulu /******************************************************************************* 32*91f16700Schasinglulu * CPU Extended Control register specific definitions. 33*91f16700Schasinglulu ******************************************************************************/ 34*91f16700Schasinglulu #define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24) 37*91f16700Schasinglulu #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) 38*91f16700Schasinglulu 39*91f16700Schasinglulu /******************************************************************************* 40*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 41*91f16700Schasinglulu ******************************************************************************/ 42*91f16700Schasinglulu #define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0 43*91f16700Schasinglulu 44*91f16700Schasinglulu #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 45*91f16700Schasinglulu #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1 48*91f16700Schasinglulu 49*91f16700Schasinglulu #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 50*91f16700Schasinglulu #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 51*91f16700Schasinglulu #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 52*91f16700Schasinglulu #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 53*91f16700Schasinglulu #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 54*91f16700Schasinglulu #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 55*91f16700Schasinglulu 56*91f16700Schasinglulu #define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2 57*91f16700Schasinglulu 58*91f16700Schasinglulu #define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 59*91f16700Schasinglulu 60*91f16700Schasinglulu /* Instruction patching registers */ 61*91f16700Schasinglulu #define CPUPSELR_EL3 S3_6_C15_C8_0 62*91f16700Schasinglulu #define CPUPCR_EL3 S3_6_C15_C8_1 63*91f16700Schasinglulu #define CPUPOR_EL3 S3_6_C15_C8_2 64*91f16700Schasinglulu #define CPUPMR_EL3 S3_6_C15_C8_3 65*91f16700Schasinglulu 66*91f16700Schasinglulu #endif /* RAINIER_H */ 67