1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef NEOVERSE_V2_H 8*91f16700Schasinglulu #define NEOVERSE_V2_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define NEOVERSE_V2_MIDR U(0x410FD4F0) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Neoverse V2 loop count for CVE-2022-23960 mitigation */ 13*91f16700Schasinglulu #define NEOVERSE_V2_BHB_LOOP_COUNT U(132) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 19*91f16700Schasinglulu 20*91f16700Schasinglulu /******************************************************************************* 21*91f16700Schasinglulu * CPU Power Control register specific definitions 22*91f16700Schasinglulu ******************************************************************************/ 23*91f16700Schasinglulu #define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24*91f16700Schasinglulu #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25*91f16700Schasinglulu 26*91f16700Schasinglulu /******************************************************************************* 27*91f16700Schasinglulu * CPU Extended Control register 2 specific definitions. 28*91f16700Schasinglulu ******************************************************************************/ 29*91f16700Schasinglulu #define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 30*91f16700Schasinglulu #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 31*91f16700Schasinglulu #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) 32*91f16700Schasinglulu #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 33*91f16700Schasinglulu 34*91f16700Schasinglulu /******************************************************************************* 35*91f16700Schasinglulu * CPU Auxiliary Control register 2 specific definitions. 36*91f16700Schasinglulu ******************************************************************************/ 37*91f16700Schasinglulu #define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 38*91f16700Schasinglulu #define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 39*91f16700Schasinglulu 40*91f16700Schasinglulu /******************************************************************************* 41*91f16700Schasinglulu * CPU Auxiliary Control register 3 specific definitions. 42*91f16700Schasinglulu ******************************************************************************/ 43*91f16700Schasinglulu #define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 44*91f16700Schasinglulu #define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 45*91f16700Schasinglulu 46*91f16700Schasinglulu /******************************************************************************* 47*91f16700Schasinglulu * CPU Auxiliary Control register 5 specific definitions. 48*91f16700Schasinglulu ******************************************************************************/ 49*91f16700Schasinglulu #define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0 50*91f16700Schasinglulu #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 51*91f16700Schasinglulu #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 52*91f16700Schasinglulu 53*91f16700Schasinglulu #endif /* NEOVERSE_V2_H */ 54