1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef NEOVERSE_V1_H 8*91f16700Schasinglulu #define NEOVERSE_V1_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define NEOVERSE_V1_MIDR U(0x410FD400) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Neoverse V1 loop count for CVE-2022-23960 mitigation */ 13*91f16700Schasinglulu #define NEOVERSE_V1_BHB_LOOP_COUNT U(32) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions. 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 19*91f16700Schasinglulu #define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0 20*91f16700Schasinglulu #define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2 21*91f16700Schasinglulu #define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3 22*91f16700Schasinglulu #define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 23*91f16700Schasinglulu #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 24*91f16700Schasinglulu #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 25*91f16700Schasinglulu #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) 26*91f16700Schasinglulu #define CPUECTLR_EL1_PF_MODE_LSB U(6) 27*91f16700Schasinglulu #define CPUECTLR_EL1_PF_MODE_WIDTH U(2) 28*91f16700Schasinglulu 29*91f16700Schasinglulu /******************************************************************************* 30*91f16700Schasinglulu * CPU Power Control register specific definitions 31*91f16700Schasinglulu ******************************************************************************/ 32*91f16700Schasinglulu #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 33*91f16700Schasinglulu #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 34*91f16700Schasinglulu 35*91f16700Schasinglulu /******************************************************************************* 36*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 37*91f16700Schasinglulu ******************************************************************************/ 38*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 39*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1) 40*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 41*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) 42*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) 43*91f16700Schasinglulu 44*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2 45*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47) 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0 48*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55) 49*91f16700Schasinglulu #define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56) 50*91f16700Schasinglulu 51*91f16700Schasinglulu #endif /* NEOVERSE_V1_H */ 52