1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef NEOVERSE_POSEIDON_H 8*91f16700Schasinglulu #define NEOVERSE_POSEIDON_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define NEOVERSE_POSEIDON_MIDR U(0x410FD830) 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */ 14*91f16700Schasinglulu #define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /******************************************************************************* 17*91f16700Schasinglulu * CPU Extended Control register specific definitions. 18*91f16700Schasinglulu ******************************************************************************/ 19*91f16700Schasinglulu #define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * CPU Power Control register specific definitions 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25*91f16700Schasinglulu #define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 26*91f16700Schasinglulu 27*91f16700Schasinglulu #endif /* NEOVERSE_POSEIDON_H */ 28