1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef NEOVERSE_N_COMMON_H 8*91f16700Schasinglulu #define NEOVERSE_N_COMMON_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /****************************************************************************** 11*91f16700Schasinglulu * Neoverse Nx CPU Configuration register definitions 12*91f16700Schasinglulu *****************************************************************************/ 13*91f16700Schasinglulu #define CPUCFR_EL1 S3_0_C15_C0_0 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* SCU bit of CPU Configuration Register, EL1 */ 16*91f16700Schasinglulu #define SCU_SHIFT U(2) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #endif /* NEOVERSE_N_COMMON_H */ 19