1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef NEOVERSE_N2_H 8*91f16700Schasinglulu #define NEOVERSE_N2_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Neoverse N2 ID register for revision r0p0 */ 11*91f16700Schasinglulu #define NEOVERSE_N2_MIDR U(0x410FD490) 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Neoverse N2 loop count for CVE-2022-23960 mitigation */ 14*91f16700Schasinglulu #define NEOVERSE_N2_BHB_LOOP_COUNT U(32) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /******************************************************************************* 17*91f16700Schasinglulu * CPU Power control register 18*91f16700Schasinglulu ******************************************************************************/ 19*91f16700Schasinglulu #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 20*91f16700Schasinglulu #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 21*91f16700Schasinglulu 22*91f16700Schasinglulu /******************************************************************************* 23*91f16700Schasinglulu * CPU Extended Control register specific definitions. 24*91f16700Schasinglulu ******************************************************************************/ 25*91f16700Schasinglulu #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 26*91f16700Schasinglulu #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 27*91f16700Schasinglulu #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 28*91f16700Schasinglulu 29*91f16700Schasinglulu /******************************************************************************* 30*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 31*91f16700Schasinglulu ******************************************************************************/ 32*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 33*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 34*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 35*91f16700Schasinglulu 36*91f16700Schasinglulu /******************************************************************************* 37*91f16700Schasinglulu * CPU Auxiliary Control register 2 specific definitions. 38*91f16700Schasinglulu ******************************************************************************/ 39*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 40*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 41*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 42*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 43*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 44*91f16700Schasinglulu 45*91f16700Schasinglulu /******************************************************************************* 46*91f16700Schasinglulu * CPU Auxiliary Control register 3 specific definitions. 47*91f16700Schasinglulu ******************************************************************************/ 48*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2 49*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 50*91f16700Schasinglulu 51*91f16700Schasinglulu /******************************************************************************* 52*91f16700Schasinglulu * CPU Auxiliary Control register 5 specific definitions. 53*91f16700Schasinglulu ******************************************************************************/ 54*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 55*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 56*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 57*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 58*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 59*91f16700Schasinglulu #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 60*91f16700Schasinglulu 61*91f16700Schasinglulu /******************************************************************************* 62*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 63*91f16700Schasinglulu ******************************************************************************/ 64*91f16700Schasinglulu #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 65*91f16700Schasinglulu #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 66*91f16700Schasinglulu #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 67*91f16700Schasinglulu #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 68*91f16700Schasinglulu #define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) 69*91f16700Schasinglulu #define CPUECTLR2_EL1_TXREQ_LSB U(0) 70*91f16700Schasinglulu #define CPUECTLR2_EL1_TXREQ_WIDTH U(3) 71*91f16700Schasinglulu 72*91f16700Schasinglulu #endif /* NEOVERSE_N2_H */ 73