1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef NEOVERSE_N1_H 8*91f16700Schasinglulu #define NEOVERSE_N1_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Neoverse N1 MIDR for revision 0 */ 13*91f16700Schasinglulu #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Neoverse N1 loop count for CVE-2022-23960 mitigation */ 16*91f16700Schasinglulu #define NEOVERSE_N1_BHB_LOOP_COUNT U(24) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* Exception Syndrome register EC code for IC Trap */ 19*91f16700Schasinglulu #define NEOVERSE_N1_EC_IC_TRAP U(0x1f) 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * CPU Power Control register specific definitions. 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 27*91f16700Schasinglulu #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 32*91f16700Schasinglulu #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 33*91f16700Schasinglulu 34*91f16700Schasinglulu /******************************************************************************* 35*91f16700Schasinglulu * CPU Extended Control register specific definitions. 36*91f16700Schasinglulu ******************************************************************************/ 37*91f16700Schasinglulu #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 38*91f16700Schasinglulu 39*91f16700Schasinglulu #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) 40*91f16700Schasinglulu #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) 41*91f16700Schasinglulu #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 42*91f16700Schasinglulu 43*91f16700Schasinglulu /******************************************************************************* 44*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 45*91f16700Schasinglulu ******************************************************************************/ 46*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 47*91f16700Schasinglulu 48*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 49*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 50*91f16700Schasinglulu 51*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 54*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 55*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 56*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 57*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 58*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 59*91f16700Schasinglulu 60*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 61*91f16700Schasinglulu 62*91f16700Schasinglulu #define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 63*91f16700Schasinglulu 64*91f16700Schasinglulu /* Instruction patching registers */ 65*91f16700Schasinglulu #define CPUPSELR_EL3 S3_6_C15_C8_0 66*91f16700Schasinglulu #define CPUPCR_EL3 S3_6_C15_C8_1 67*91f16700Schasinglulu #define CPUPOR_EL3 S3_6_C15_C8_2 68*91f16700Schasinglulu #define CPUPMR_EL3 S3_6_C15_C8_3 69*91f16700Schasinglulu 70*91f16700Schasinglulu #endif /* NEOVERSE_N1_H */ 71