1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef NEOVERSE_E1_H 8*91f16700Schasinglulu #define NEOVERSE_E1_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define NEOVERSE_E1_MIDR U(0x410FD4A0) 13*91f16700Schasinglulu 14*91f16700Schasinglulu /******************************************************************************* 15*91f16700Schasinglulu * CPU Extended Control register specific definitions. 16*91f16700Schasinglulu ******************************************************************************/ 17*91f16700Schasinglulu #define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 18*91f16700Schasinglulu 19*91f16700Schasinglulu /******************************************************************************* 20*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 21*91f16700Schasinglulu ******************************************************************************/ 22*91f16700Schasinglulu #define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 23*91f16700Schasinglulu 24*91f16700Schasinglulu /******************************************************************************* 25*91f16700Schasinglulu * CPU Power Control register specific definitions. 26*91f16700Schasinglulu ******************************************************************************/ 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29*91f16700Schasinglulu #define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #endif /* NEOVERSE_E1_H */ 32