1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef DSU_DEF_H 8*91f16700Schasinglulu #define DSU_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************** 13*91f16700Schasinglulu * DSU Cluster Configuration registers definitions 14*91f16700Schasinglulu ********************************************************************/ 15*91f16700Schasinglulu #define CLUSTERCFR_EL1 S3_0_C15_C3_0 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define CLUSTERCFR_ACP_SHIFT U(11) 18*91f16700Schasinglulu 19*91f16700Schasinglulu /******************************************************************** 20*91f16700Schasinglulu * DSU Cluster Main Revision ID registers definitions 21*91f16700Schasinglulu ********************************************************************/ 22*91f16700Schasinglulu #define CLUSTERIDR_EL1 S3_0_C15_C3_1 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define CLUSTERIDR_REV_SHIFT U(0) 25*91f16700Schasinglulu #define CLUSTERIDR_REV_BITS U(4) 26*91f16700Schasinglulu #define CLUSTERIDR_VAR_SHIFT U(4) 27*91f16700Schasinglulu #define CLUSTERIDR_VAR_BITS U(4) 28*91f16700Schasinglulu 29*91f16700Schasinglulu /******************************************************************** 30*91f16700Schasinglulu * DSU Cluster Auxiliary Control registers definitions 31*91f16700Schasinglulu ********************************************************************/ 32*91f16700Schasinglulu #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) 35*91f16700Schasinglulu #define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************** 38*91f16700Schasinglulu * Masks applied for DSU errata workarounds 39*91f16700Schasinglulu ********************************************************************/ 40*91f16700Schasinglulu #define DSU_ERRATA_936184_MASK (U(0x3) << 15) 41*91f16700Schasinglulu 42*91f16700Schasinglulu #endif /* DSU_DEF_H */ 43