1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef DENVER_H 8*91f16700Schasinglulu #define DENVER_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* MIDR values for Denver */ 11*91f16700Schasinglulu #define DENVER_MIDR_PN0 U(0x4E0F0000) 12*91f16700Schasinglulu #define DENVER_MIDR_PN1 U(0x4E0F0010) 13*91f16700Schasinglulu #define DENVER_MIDR_PN2 U(0x4E0F0020) 14*91f16700Schasinglulu #define DENVER_MIDR_PN3 U(0x4E0F0030) 15*91f16700Schasinglulu #define DENVER_MIDR_PN4 U(0x4E0F0040) 16*91f16700Schasinglulu #define DENVER_MIDR_PN5 U(0x4E0F0050) 17*91f16700Schasinglulu #define DENVER_MIDR_PN6 U(0x4E0F0060) 18*91f16700Schasinglulu #define DENVER_MIDR_PN7 U(0x4E0F0070) 19*91f16700Schasinglulu #define DENVER_MIDR_PN8 U(0x4E0F0080) 20*91f16700Schasinglulu #define DENVER_MIDR_PN9 U(0x4E0F0090) 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* Implementer code in the MIDR register */ 23*91f16700Schasinglulu #define DENVER_IMPL U(0x4E) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* CPU state ids - implementation defined */ 26*91f16700Schasinglulu #define DENVER_CPU_STATE_POWER_DOWN U(0x3) 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* Speculative store buffering */ 29*91f16700Schasinglulu #define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11) 30*91f16700Schasinglulu #define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18) 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* Speculative memory disambiguation */ 33*91f16700Schasinglulu #define DENVER_CPU_DIS_MD_EL3 (U(1) << 9) 34*91f16700Schasinglulu #define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17) 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* Core power management states */ 37*91f16700Schasinglulu #define DENVER_CPU_PMSTATE_C1 U(0x1) 38*91f16700Schasinglulu #define DENVER_CPU_PMSTATE_C6 U(0x6) 39*91f16700Schasinglulu #define DENVER_CPU_PMSTATE_C7 U(0x7) 40*91f16700Schasinglulu #define DENVER_CPU_PMSTATE_MASK U(0xF) 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* ACTRL_ELx bits to enable dual execution*/ 43*91f16700Schasinglulu #define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9) 44*91f16700Schasinglulu #define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9) 45*91f16700Schasinglulu #define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4) 46*91f16700Schasinglulu 47*91f16700Schasinglulu #ifndef __ASSEMBLER__ 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* Disable Dynamic Code Optimisation */ 50*91f16700Schasinglulu void denver_disable_dco(void); 51*91f16700Schasinglulu 52*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 53*91f16700Schasinglulu 54*91f16700Schasinglulu #endif /* DENVER_H */ 55