1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CPUAMU_H 8*91f16700Schasinglulu #define CPUAMU_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /******************************************************************************* 11*91f16700Schasinglulu * CPU Activity Monitor Unit register specific definitions. 12*91f16700Schasinglulu ******************************************************************************/ 13*91f16700Schasinglulu #define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7 14*91f16700Schasinglulu #define CPUAMCNTENSET_EL0 S3_3_C15_C9_6 15*91f16700Schasinglulu #define CPUAMCFGR_EL0 S3_3_C15_C10_6 16*91f16700Schasinglulu #define CPUAMUSERENR_EL0 S3_3_C15_C10_7 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* Activity Monitor Event Counter Registers */ 19*91f16700Schasinglulu #define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0 20*91f16700Schasinglulu #define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1 21*91f16700Schasinglulu #define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2 22*91f16700Schasinglulu #define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3 23*91f16700Schasinglulu #define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* Activity Monitor Event Type Registers */ 26*91f16700Schasinglulu #define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0 27*91f16700Schasinglulu #define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1 28*91f16700Schasinglulu #define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2 29*91f16700Schasinglulu #define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3 30*91f16700Schasinglulu #define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4 31*91f16700Schasinglulu 32*91f16700Schasinglulu #ifndef __ASSEMBLER__ 33*91f16700Schasinglulu #include <stdint.h> 34*91f16700Schasinglulu 35*91f16700Schasinglulu uint64_t cpuamu_cnt_read(unsigned int idx); 36*91f16700Schasinglulu void cpuamu_cnt_write(unsigned int idx, uint64_t val); 37*91f16700Schasinglulu unsigned int cpuamu_read_cpuamcntenset_el0(void); 38*91f16700Schasinglulu unsigned int cpuamu_read_cpuamcntenclr_el0(void); 39*91f16700Schasinglulu void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 40*91f16700Schasinglulu void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 41*91f16700Schasinglulu 42*91f16700Schasinglulu int midr_match(unsigned int cpu_midr); 43*91f16700Schasinglulu void cpuamu_context_save(unsigned int nr_counters); 44*91f16700Schasinglulu void cpuamu_context_restore(unsigned int nr_counters); 45*91f16700Schasinglulu 46*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 47*91f16700Schasinglulu 48*91f16700Schasinglulu #endif /* CPUAMU_H */ 49