1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_X4_H 8*91f16700Schasinglulu #define CORTEX_X4_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define CORTEX_X4_MIDR U(0x410FD821) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex X4 loop count for CVE-2022-23960 mitigation */ 13*91f16700Schasinglulu #define CORTEX_X4_BHB_LOOP_COUNT U(132) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4 19*91f16700Schasinglulu 20*91f16700Schasinglulu /******************************************************************************* 21*91f16700Schasinglulu * CPU Power Control register specific definitions 22*91f16700Schasinglulu ******************************************************************************/ 23*91f16700Schasinglulu #define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24*91f16700Schasinglulu #define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #endif /* CORTEX_X4_H */ 27