1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_X3_H 8*91f16700Schasinglulu #define CORTEX_X3_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define CORTEX_X3_MIDR U(0x410FD4E0) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-X3 loop count for CVE-2022-23960 mitigation */ 13*91f16700Schasinglulu #define CORTEX_X3_BHB_LOOP_COUNT U(132) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4 19*91f16700Schasinglulu 20*91f16700Schasinglulu /******************************************************************************* 21*91f16700Schasinglulu * CPU Power Control register specific definitions 22*91f16700Schasinglulu ******************************************************************************/ 23*91f16700Schasinglulu #define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24*91f16700Schasinglulu #define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25*91f16700Schasinglulu #define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4) 26*91f16700Schasinglulu #define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7) 27*91f16700Schasinglulu 28*91f16700Schasinglulu /******************************************************************************* 29*91f16700Schasinglulu * CPU Auxiliary Control register 2 specific definitions. 30*91f16700Schasinglulu ******************************************************************************/ 31*91f16700Schasinglulu #define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 32*91f16700Schasinglulu #define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 33*91f16700Schasinglulu 34*91f16700Schasinglulu /******************************************************************************* 35*91f16700Schasinglulu * CPU Auxiliary Control register 5 specific definitions. 36*91f16700Schasinglulu ******************************************************************************/ 37*91f16700Schasinglulu #define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0 38*91f16700Schasinglulu #define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 39*91f16700Schasinglulu #define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 40*91f16700Schasinglulu 41*91f16700Schasinglulu /******************************************************************************* 42*91f16700Schasinglulu * CPU Extended Control register 2 specific definitions. 43*91f16700Schasinglulu ******************************************************************************/ 44*91f16700Schasinglulu #define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 45*91f16700Schasinglulu 46*91f16700Schasinglulu #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) 47*91f16700Schasinglulu #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 48*91f16700Schasinglulu #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) 49*91f16700Schasinglulu 50*91f16700Schasinglulu #endif /* CORTEX_X3_H */ 51