1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_X2_H 8*91f16700Schasinglulu #define CORTEX_X2_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define CORTEX_X2_MIDR U(0x410FD480) 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Cortex-X2 loop count for CVE-2022-23960 mitigation */ 13*91f16700Schasinglulu #define CORTEX_X2_BHB_LOOP_COUNT U(32) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * CPU Extended Control register specific definitions 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 19*91f16700Schasinglulu #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * CPU Extended Control register 2 specific definitions 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu #define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) 27*91f16700Schasinglulu #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 28*91f16700Schasinglulu #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) 29*91f16700Schasinglulu 30*91f16700Schasinglulu /******************************************************************************* 31*91f16700Schasinglulu * CPU Power Control register specific definitions 32*91f16700Schasinglulu ******************************************************************************/ 33*91f16700Schasinglulu #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 34*91f16700Schasinglulu #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 35*91f16700Schasinglulu 36*91f16700Schasinglulu /******************************************************************************* 37*91f16700Schasinglulu * CPU Auxiliary Control Register definitions 38*91f16700Schasinglulu ******************************************************************************/ 39*91f16700Schasinglulu #define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 40*91f16700Schasinglulu #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * CPU Auxiliary Control Register 2 definitions 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu #define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 46*91f16700Schasinglulu #define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 47*91f16700Schasinglulu 48*91f16700Schasinglulu /******************************************************************************* 49*91f16700Schasinglulu * CPU Auxiliary Control Register 5 definitions 50*91f16700Schasinglulu ******************************************************************************/ 51*91f16700Schasinglulu #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 52*91f16700Schasinglulu #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 53*91f16700Schasinglulu 54*91f16700Schasinglulu /******************************************************************************* 55*91f16700Schasinglulu * CPU Implementation Specific Selected Instruction registers 56*91f16700Schasinglulu ******************************************************************************/ 57*91f16700Schasinglulu #define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 58*91f16700Schasinglulu #define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 59*91f16700Schasinglulu #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 60*91f16700Schasinglulu #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 61*91f16700Schasinglulu 62*91f16700Schasinglulu #endif /* CORTEX_X2_H */ 63