1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, Google LLC. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_X1_H 8*91f16700Schasinglulu #define CORTEX_X1_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Cortex-X1 MIDR for r1p0 */ 11*91f16700Schasinglulu #define CORTEX_X1_MIDR U(0x411fd440) 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Cortex-X1 loop count for CVE-2022-23960 mitigation */ 14*91f16700Schasinglulu #define CORTEX_X1_BHB_LOOP_COUNT U(32) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /******************************************************************************* 17*91f16700Schasinglulu * CPU Extended Control register specific definitions. 18*91f16700Schasinglulu ******************************************************************************/ 19*91f16700Schasinglulu #define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * CPU Auxiliary Control register specific definitions. 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu #define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1 25*91f16700Schasinglulu 26*91f16700Schasinglulu /******************************************************************************* 27*91f16700Schasinglulu * CPU Power Control register specific definitions 28*91f16700Schasinglulu ******************************************************************************/ 29*91f16700Schasinglulu #define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 30*91f16700Schasinglulu #define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1) 31*91f16700Schasinglulu 32*91f16700Schasinglulu #endif /* CORTEX_X1_H */ 33