1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_GELAS_H 8*91f16700Schasinglulu #define CORTEX_GELAS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define CORTEX_GELAS_MIDR U(0x410FD8B0) 13*91f16700Schasinglulu 14*91f16700Schasinglulu /******************************************************************************* 15*91f16700Schasinglulu * CPU Extended Control register specific definitions 16*91f16700Schasinglulu ******************************************************************************/ 17*91f16700Schasinglulu #define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5 18*91f16700Schasinglulu 19*91f16700Schasinglulu /******************************************************************************* 20*91f16700Schasinglulu * CPU Power Control register specific definitions 21*91f16700Schasinglulu ******************************************************************************/ 22*91f16700Schasinglulu #define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 23*91f16700Schasinglulu #define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * SME Control registers 27*91f16700Schasinglulu ******************************************************************************/ 28*91f16700Schasinglulu #define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3 29*91f16700Schasinglulu #define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3 30*91f16700Schasinglulu 31*91f16700Schasinglulu #endif /* CORTEX_GELAS_H */ 32