1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CORTEX_A78C_H 8*91f16700Schasinglulu #define CORTEX_A78C_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define CORTEX_A78C_MIDR U(0x410FD4B1) 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 14*91f16700Schasinglulu #define CORTEX_A78C_BHB_LOOP_COUNT U(32) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /******************************************************************************* 17*91f16700Schasinglulu * CPU Auxiliary Control register 2 specific definitions. 18*91f16700Schasinglulu * ****************************************************************************/ 19*91f16700Schasinglulu #define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 20*91f16700Schasinglulu #define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 21*91f16700Schasinglulu #define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 22*91f16700Schasinglulu 23*91f16700Schasinglulu /******************************************************************************* 24*91f16700Schasinglulu * CPU Extended Control register specific definitions. 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 27*91f16700Schasinglulu #define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) 28*91f16700Schasinglulu #define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) 29*91f16700Schasinglulu #define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) 30*91f16700Schasinglulu 31*91f16700Schasinglulu /******************************************************************************* 32*91f16700Schasinglulu * CPU Power Control register specific definitions 33*91f16700Schasinglulu ******************************************************************************/ 34*91f16700Schasinglulu #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 35*91f16700Schasinglulu #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************************* 38*91f16700Schasinglulu * CPU Auxiliary Control register 3 specific definitions. 39*91f16700Schasinglulu ******************************************************************************/ 40*91f16700Schasinglulu #define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * CPU Implementation Specific Selected Instruction registers 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu #define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 46*91f16700Schasinglulu #define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 47*91f16700Schasinglulu #define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 48*91f16700Schasinglulu #define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 49*91f16700Schasinglulu 50*91f16700Schasinglulu #endif /* CORTEX_A78C_H */ 51