1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef CORTEX_A78_AE_H 9*91f16700Schasinglulu #define CORTEX_A78_AE_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <cortex_a78.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define CORTEX_A78_AE_MIDR U(0x410FD420) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Cortex-A78AE loop count for CVE-2022-23960 mitigation */ 16*91f16700Schasinglulu #define CORTEX_A78_AE_BHB_LOOP_COUNT U(32) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * CPU Extended Control register specific definitions. 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu #define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1 22*91f16700Schasinglulu #define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8 23*91f16700Schasinglulu 24*91f16700Schasinglulu /******************************************************************************* 25*91f16700Schasinglulu * CPU Auxiliary Control register 2 specific definitions. 26*91f16700Schasinglulu ******************************************************************************/ 27*91f16700Schasinglulu #define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1 28*91f16700Schasinglulu #define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0 29*91f16700Schasinglulu #define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40 30*91f16700Schasinglulu 31*91f16700Schasinglulu #endif /* CORTEX_A78_AE_H */ 32